ADN2817 Analog Devices, Inc., ADN2817 Datasheet - Page 24

• Manufacturer Part Number: ADN2817
• Description: Continuous Rate 10 Mbps To 2.7gb/s Clock And Data Recovery Ics
• Manufacturer: Analog Devices, Inc.

ADN2817/ADN2818
PRBS Generator/Detector
The ADN2817/ADN2818 has an integrated PRBS generator/
detector for system testing purposes. The device is configurable
as either a PRBS detector or a PRBS generator. The two functions
cannot be used at the same time.
The following steps configure the PRBS detector (PRBS 7 only):
1.
2.
The PRBS error signal outputs on the DATAOUTP/DATAOUTN
pins. Every time the PRBS detector detects an error, the
DATAOUTP/DATAOUTN outputs pulse twice to a Logic 1,
that is, DATAOUTP = 1, DATAOUTN = 0.
The following steps configure the PRBS generator (PRBS 7 only):
1.
2.
3.
Note that the PRBS generator is clocked by the VCO; therefore,
the user needs to feed in a clock at half the desired frequency.
For example, for an OC-48 PRBS pattern, input a 1.244 GHz
clock to PIN/NIN. This appears as a 2.488 Gbps NRZ data
pattern to the ADN2817/ADN2818. The recovered clock is
2.488 GHz, which clocks the PRBS generator to produce an
OC-48 PRBS pattern on the outputs.
Set CTRLE[2:0] = 0x5.
Set CTRLD[2:0] = 0x4 to enable the PRBS detector.
Set CTRLE[2:0] = 0x5.
Set CTRLD[2:0] = 0x1 to enable the PRBS generator.
Write a 1 to 0 transition into CTRLD[3] to initiate a
PRBS 7 pattern.
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CLK Holdover Mode
This mode of operation is available in LTD mode. In CLK
holdover mode, the output clock frequency remains within
±5% if the input data is removed or changed. To operate in
this mode, the user writes to the I
holdover mode by setting SEL_MODE[1] = 1. The user must
then initiate a frequency acquisition by writing a 1 to 0 transi-
tion into CTRLB[5], at which time the device locks onto the
input data rate. At this point, the output frequency remains
within ±5% of the initial acquired value regardless of whether
the input data is removed or the data rate changes.
It is important to note that all frequency acquisitions in this
mode must be initiated by writing a 1 to 0 transition into
CTRLB[5]. In this mode, the device does not automatically
initiate a new frequency acquisition when the input is momen-
tarily interrupted or if the input data rate changes.
CDR Bypass Mode
The CDR on the ADN2817/ADN2818 can be bypassed by setting
Bit CTRLD[7] = 1. In this mode, the ADN2817/ADN2818 feed
the input directly through the input amplifiers to the output
buffer, completely bypassing the CDR.
Disable Output Buffers
The ADN2817/ADN2818 provide the option of disabling the
output buffers for power savings. The clock output buffers
can be disabled by setting Bit CTRLD[5] = 1. This reduces
the total power consumption of the device by ~100 mW. For
an additional 100 mW power savings, such as in low power
standby mode, the data output buffers can also be disabled by
setting Bit CTRLD[6] = 1.
2
C to put the part into CLK