ADN2817 Analog Devices, Inc., ADN2817 Datasheet - Page 27

• Manufacturer Part Number: ADN2817
• Description: Continuous Rate 10 Mbps To 2.7gb/s Clock And Data Recovery Ics
• Manufacturer: Analog Devices, Inc.

DC-COUPLED APPLICATION
The inputs to the ADN2817/ADN2818 can also be dc-coupled.
This can be necessary in burst mode applications with long
periods of CIDs and where baseline wander cannot be tolerated.
If the inputs to the ADN2817/ADN2818 are dc-coupled, care must
be taken not to violate the input range and common-mode level
requirements of the ADN2817/ADN2818 (see Figure 39 through
Figure 41). If dc coupling is required, and the output levels of
the TIA do not adhere to the levels shown in Figure 40, then
level shifting and/or attenuation must occur between the TIA
outputs and the ADN2817/ADN2818 inputs.
VCC
VDIFF
VDIFF = V2 – V2b
VTH = ADN2817 QUANTIZER THRESHOLD
NOTES
1. DURING THE DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE VREF
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2817. THE
TIA
V2b
V1b
LEVEL WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER
HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER DOES NOT
RECOGNIZE THIS AS A VALID STATE.
QUANTIZER RECOGNIZES BOTH HIGH AND LOW STATES AT THIS POINT.
TIA
V2
V1
Figure 39. DC-Coupled Application
1
VCC
0.1µF
50Ω
TIA
NIN
PIN
V1b
V1
VREF
ADN2817/ADN2818
50Ω
C
IN
2
50Ω
V2b
V2
3kΩ
NIN
2.5V
PIN
Figure 38. Example of Baseline Wander
50Ω
50Ω
V
REF
Rev. 0 | Page 27 of 36
LIMAMP
ADN2817
3
CDR
Figure 41. Maximum Allowed DC-Coupled Input Levels
NIN
Figure 40. Minimum Allowed DC-Coupled Input Levels
PIN
C
PIN
NIN
OUT
4
DATAOUTP
DATAOUTN
V p-p = PIN – NIN = 2 × V
V p-p = PIN – NIN = 2 × V
ADN2817/ADN2818
SE
SE
VREF
VTH
= 10mV AT SENSITIVITY
= 2.0V MAX
V
SE
V
V
(DC-COUPLED)
SE
CM
V
(DC-COUPLED)
= 1.0V MAX
CM
= 5mV MIN
= 2.3V
= 2.3V MIN