RC28F256 Intel Corporation, RC28F256 Datasheet - Page 58

• Manufacturer Part Number: RC28F256
• Description: Intel StrataFlash Embedded Memory
• Manufacturer: Intel Corporation

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1-Gbit P30 Family
10.3.4
Figure 30.
April 2005
58
Data Hold
Data Hold
1 CLK
2 CLK
Table 24.
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid
on DQ[15:0] for one or two clock cycles. This period of time is called the “data cycle”. When DH
is set, output data is held for two clocks (default). When DH is cleared, output data is held for one
clock (see
delay should be considered when determining whether to hold output data for one or two clocks. A
method for determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition must be
satisfied:
For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming
t
The equation is satisfied and data will be available at every clock period with data hold setting at
one clock. If t
must be used.
Data Hold Timing
CHQV
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
CE# =’0’, OE# = ‘0’
Synchronous Array Reads
Synchronous Non-Array Reads
All Asynchronous Reads
All Writes
Notes:
1.
2.
= 20 ns and t
Active: WAIT is asserted until data becomes valid, then deasserts
When OE# = V
t
t
DATA
20 ns + 4 ns
CHQV
Figure
D[15:0] [Q]
D[15:0] [Q]
CHQV
= Data set up to Clock (defined by CPU)
CLK [C]
WAIT Functionality Table
(ns) + t
Intel StrataFlash
Condition
30). The processor’s data setup time and the flash memory’s clock-to-data output
DATA
(ns) + t
Order Number: 306666, Revision: 001
IH
≤
during writes, WAIT = High-Z
DATA
25 ns
= 4 ns. Applying these values to the formula above:
DATA
(ns)
(ns) > One CLK Period (ns), data hold setting of 2 clock periods
≤
®
One CLK Period (ns)
Embedded Memory (P30)
Output
Valid
High-Z
Active
Active
Active
Deasserted
High-Z
Output
Valid
Output
Valid
WAIT
Output
Valid
Output
Notes
Valid
1,2
1
1
1
1
1
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