CD016G0PFA Advanced Micro Devices, Inc., CD016G0PFA Datasheet - Page 15

• Manufacturer Part Number: CD016G0PFA
• Description: 16 Megabit(512 K X 32-Bit),CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/write Flash Memory
• Manufacturer: Advanced Micro Devices, Inc.

March 22, 2004 S29CD016_00A0
VersatileI/O™ (V
Requirements for Reading Array Data
Simultaneous Read/Write
Operations Overview and Restrictions
The VersatileI/O (V
the device generates at its data outputs and the voltages tolerated at its data in-
puts to the same voltage level that is asserted on the V
The output voltage generated on the device is determined based on the V
(V
A V
level.
A V
To read array data from the outputs, the system must drive the CE# and OE#
pins to V
control and gates array data to the output pins. WE# should remain at V
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the command register
contents are altered.
Address access time (t
data. The chip enable access time (t
stable CE# to valid data at the output pins. The output enable access time (t
is the delay from the falling edge of OE# to valid data at the output pins (assum-
ing the addresses have been stable for at least t
asserted for at least t
See “Reading Array Data” for more information. Refer to the AC Read Operations
table for timing specifications and to 15 for the timing diagram. I
Characteristics table represents the active current specification for reading array
data.
Overview
The Simultaneous Read/Write feature allows an program or erase operation to be
executed in one (busy) bank, while performing other operations in the other bank
(non-busy).
The Simultaneous Read/Write operation of this device has been optimized for ap-
plications that could most benefit from this capability. These applications store
code in the larger bank, while storing data in the smaller bank. The best example
of this is when a Sector Erase Operation (as an embedded operation) in the
smaller (busy) bank, while performing a Burst/synchronous Read Operation in
the larger (non-busy) bank.
Restrictions
The Simultaneous Read/Write function is tested by executing an embedded op-
eration in the small (busy) bank while performing other operations in the big
(non-busy) bank. However, the opposite case is neither tested nor valid. That is,
CCQ
CC
IO
) level.
of 1.65–1.95 volts is targeted to provide for I/O tolerance at the 1.8 volt
and V
IL
. CE# is the power control and selects the device. OE# is the output
A d v a n c e
IO
IO
of 2.5–2.75 volts makes the device appear as 2.5 volt-only.
) Control
IO
) control allows the host system to set the voltage levels that
CE
ACC
–t
OE
) is the delay from stable addresses to valid output
I n f o r m a t i o n
time).
S29CD016G
CE
) is the delay from stable addresses and
ACC
–t
OE
IO
time and CE# has been
pin.
CC1
in the DC
IH
.
OE
IO
)
15