CD016G0PFA Advanced Micro Devices, Inc., CD016G0PFA Datasheet - Page 34

• Manufacturer Part Number: CD016G0PFA
• Description: 16 Megabit(512 K X 32-Bit),CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/write Flash Memory
• Manufacturer: Advanced Micro Devices, Inc.

A d v a n c e
I n f o r m a t i o n
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
, CE# = V
, or WE#
IL
IH
= V
. To initiate a write cycle, CE# and WE# must be a logical zero (V
) while
IH
IL
OE# is a logical one (V
).
IH
Power-Up Write Inhibit
If WE# = CE# = V
and OE# = V
during power-up, the device does not accept
IL
IH
commands on the rising edge of WE#. The internal state machine is automatically
reset to reading array data on power-up.
V
and V
Power-up And Power-down Sequencing
CC
IO
The device imposes no restrictions on V
and V
power-up or power-down se-
CC
IO
quencing. Asserting RESET# to V
is required during the entire V
and V
IL
CC
IO
power sequence until the respective supplies reach their operating voltages.
Once, V
and V
attain their respective operating voltages, de-assertion of RE-
CC
IO
SET# to V
is permitted.
IH
34
S29CD016G
S29CD016_00A0 March 22, 2004