CD016G0PFA Advanced Micro Devices, Inc., CD016G0PFA Datasheet - Page 60

• Manufacturer Part Number: CD016G0PFA
• Description: 16 Megabit(512 K X 32-Bit),CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/write Flash Memory
• Manufacturer: Advanced Micro Devices, Inc.

60
Legend:
BA = Address of the bank that is being switched to autoselect mode,
is in bypass mode, or is being erased. Determined by A18 and A17,
see Tables 11 and 12 for more detail.
PA = Program Address (A18:A0). Addresses latch on the falling edge
of the WE# or CE# pulse, whichever happens later.
PD = Program Data (DQ31:DQ0) written to location PA. Data latches
on the rising edge of WE# or CE# pulse, whichever happens first.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Command (Notes)
Read (5)
Reset (6)
Autoselect
(7)
Program
Chip Erase
Sector Erase
Program/Erase Suspend (12)
Program/Erase Resume (13)
CFI Query (14, 15)
Accelerated Program (16)
Configuration Register Verify (15)
Configuration Register Write (17)
Unlock Bypass Entry (18)
Unlock Bypass Program (18)
Unlock Bypass Erase (18)
Unlock Bypass CFI (14, 18)
Unlock Bypass Reset (18)
See Table 1 for description of bus operations.
All values are in hexadecimal.
Shaded cells in table denote read cycles. All other cycles are
write operations.
During unlock cycles, (lower address bits are 555 or 2AAh as
shown in table) address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
No unlock or command cycles required when bank is reading
array data.
The Reset command is required to return to the read mode (or
to the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high
(while the bank is providing status information).
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID or device ID information. See the
Command
This command cannot be executed until The Unlock Bypass
command must be executed before writing this command
sequence. The Unlock Bypass Reset command must be executed
to return to normal operation.
section for more information.
Manufacturer ID
Device ID (11)
Table 19. Memory Array Command Definitions (x32 Mode)
1
1
4
6
4
6
6
1
1
1
2
3
4
3
2
2
1
2
Addr
XXX
555
555
555
555
555
555
555
555
RA
BA
BA
55
XX
XX
XX
XX
XX
First
Data Addr
RD
AA
AA
AA
AA
AA
B0
30
98
A0
AA
AA
AA
A0
80
98
90
F0
Autoselect
A d v a n c e
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
XX
XX
PA
PA
Second
S29CD016G
Data
PD
PD
55
55
55
55
55
55
55
55
10
00
BA+555
RA = Read Address (A18:A0).
RD = Read Data (DQ31:DQ0) from location RA.
SA = Sector Address (A18:A11) for verifying (in autoselect mode),
erasing, or applying security commands.
WD = Write Data. See “Configuration Register” definition for specific
write data. Data latched on rising edge of WE#.
X = Don’t care
9.
10. Valid read operations include asynchronous and burst read mode
11. The device ID must be read across the fourth, fifth, and sixth
12. The system may read and program in non-erasing sectors, or
13. The Program/Erase Resume command is valid only during the
14. Command is valid when device is ready to read array data or
15. Asynchronous read operations.
16. ACC must be at V
17. Command is ignored during any Embedded Program, Embedded
18. The Unlock Bypass Entry command is required prior to any
Addr
555
555
555
555
555
555
555
I n f o r m a t i o n
Third
This command is ignored during any embedded program, erase
or suspended operation.
operations.
cycles. 00h in the sixth cycle indicates ordering option 00, 01h
indicates ordering option 01.
enter the autoselect mode, when in the Program/Erase Suspend
mode. The Program/Erase Suspend command is valid only
during a sector erase operation, and requires the bank address.
Erase Suspend mode, and requires the bank address.
when device is in autoselect mode.
Erase, or Suspend operation.
Unlock Bypass operation. The Unlock Bypass Reset command is
required to return to the read mode.
Bus Cycles (Notes 1–4)
Data
A0
C6
D0
90
90
80
80
20
BA+X00
BA+X01
BA+XX
Addr
555
555
XX
PA
Fourth
ID
during the entire operation of this command.
Data
WD
RD
01
7E
PD
AA
AA
BA+X0E
Addr
2AA
2AA
Fifth
S29CD016_00A0 March 22, 2004
Data
08
55
55
BA+X0F
Addr
555
SA
Sixth
Data
00/
01
10
30