CD016G0PFA Advanced Micro Devices, Inc., CD016G0PFA Datasheet - Page 22

• Manufacturer Part Number: CD016G0PFA
• Description: 16 Megabit(512 K X 32-Bit),CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/write Flash Memory
• Manufacturer: Advanced Micro Devices, Inc.

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CE# Control in Linear Mode
The CE# (Chip Enable) pin enables the device during read mode operations. CE#
must meet the required burst read setup times for burst cycle initiation. If CE#
is taken to V
mediately exits the burst sequence and floats the DQ bus and IND/WAIT# signal.
Restarting a burst cycle is accomplished by taking CE# and ADV# to V
ADV# Control In Linear Mode
The ADV# (Address Valid) pin is used to initiate a linear burst cycle at the clock
edge when CE# and ADV# are at V
burst mode operation. A burst access is initiated and the address is latched on
the first rising CLK edge when ADV# is active or upon a rising ADV# edge, which-
ever occurs first. If the ADV# signal is taken to V
burst sequence, the previous address is discarded and subsequent burst transfers
are invalid until ADV# transitions to V
burst sequence.
RESET# Control in Linear Mode
The RESET# pin immediately halts the linear burst access when taken to V
DQ data bus and IND/WAIT# signal float. Additionally, the Configuration Register
contents are reset back to the default condition where the device is placed in
asynchronous access mode.
OE# Control in Linear Mode
The OE# (Output Enable) pin is used to enable the linear burst data on the DQ
data bus and the IND/WAIT# pin. De-asserting the OE# pin to V
operation floats the data bus and the IND/WAIT# pin. However, the device will
continue to operate internally as if the burst sequence continues until the linear
burst is complete. The OE# pin does not halt the burst sequence, this is accom-
plished by either taking CE# to V
and IND/WAIT# signal remain in the float state until OE# is taken to V
IND/WAIT# Operation in Linear Mode
The IND/WAIT#, or End of Burst Indicator signal (when in linear modes), informs
the system that the last address of a burst sequence is on the DQ data bus. For
example, if a 2-double-word linear burst access is enabled using a 16-bit DQ bus
(WORD# = V
If the same scenario is usd, the IND/WAIT# signal has the same delay and setup
timing as the DQ pins. Also, the IND/WAIT# signal is controlled by the OE#
signal. If OE# is at V
at V
the end of burst sequence. The IND/WAIT# signal timing and duration is (See
“Configuration Register” for more information). The following table lists the valid
combinations of the Configuration Register bits that impact the IND/WAIT#
timing.
CC
1
1
IL
Table 7. Valid Configuration Register Bit Definition for IND/WAIT#
, the IND/WAIT# signal is driven at V
IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on risiong CLD edge
IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge
IH
IL
), the IND/WAIT# signal transitions active on the second access.
at any time during the burst linear or burst cycle, the device im-
IH
, the IND/WAIT# signal floats and is not driven. If OE#is
A d v a n c e
IH
IL
S29CD016G
or re-issuing a new ADV# pulse. The DQ bus
and the device is configured for either linear
IH
before a clock edge, which initiates a new
IH
I n f o r m a t i o n
until it transitions to V
Definition
IL
prior to the end of a linear
IH
during a burst
IL
IL
indicating
IL
.
.
IL
S29CD016_00A0 March 22, 2004
. The