CD016G0PFA Advanced Micro Devices, Inc., CD016G0PFA Datasheet - Page 20

• Manufacturer Part Number: CD016G0PFA
• Description: 16 Megabit(512 K X 32-Bit),CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/write Flash Memory
• Manufacturer: Advanced Micro Devices, Inc.

Note: Operation is shown for the 32-bit data bus.
20
IND/WAIT#
Addresses
Synchronous (Burst) Read Operation
Linear Burst Read Operations
ADV#
Data
WE#
CE#
CLK
OE#
The device is capable of performing burst read operations to improve total system
data throughput. The 2, 4, and 8 double word accesses are configurable as linear
burst accesses. All burst operations provide wrap around linear burst accesses.
Additional options for all burst modes include initial access delay configurations
(2–16 CLKs) Device configuration for burst mode operation is accomplished by
writing the Configuration Register with the desired burst configuration informa-
tion. Once the Configuration Register is written to enable burst mode operation,
all subsequent reads from the array are returned using the burst mode protocols.
Like the main memory access, the SecSi Sector memory is accessed with the
same burst or asynchronous timing as defined in the Configuration Register. How-
ever, the user must recognize burst operations past the 256 byte SecSi boundary
returns invalid data.
Burst read operations occur only to the main flash memory arrays. The Configu-
ration Register and protection bits are treated as single cycle reads, even when
burst mode is enabled. Read operations to these locations results in the data re-
maining valid while OE# is at V
to the device.
Linear burst read mode reads either 2, 4, or 8 double words (1 double word = 32
bits). (See Table 6 for all valid burst output sequences). The IND/WAIT# pin tran-
sitions active (V
before a wrap around, indicating that the system should initiate another ADV# to
start the next burst access. If the system continues to clock the device, the next
access wraps around to the starting address of the previous burst access. The
IND/WAIT# signal remains inactive (floating) when not active. See Table 6 for a
complete 32 and 16 bit data bus interface order.
Float
V
Address 0
IH
V
Address 1
OH
D0
IL
) during the last transfer of data during a linear burst read
Figure 1. Asynchronous Read Operation
Address 2
A d v a n c e
D1
IL
, regardless of the number of CLK cycles applied
S29CD016G
D2
Address 3
I n f o r m a t i o n
D3
S29CD016_00A0 March 22, 2004
D3
Float