CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 47

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
Title:
Address:
Function:
Description:
Bit
7
6
5
4
3
2
1
0
1999 Consumer Microcircuits Limited
TxDataPathQOF
TxDataPathIOF
DecimationOF
SymbolClkEn
Tx63tapOF
Tx79tapOF
TxIrqActive
TxErrorStatus
Transmit Error Status register.
$0x0E
R
This register is the Tx Data path error status register. The TxIrqActive bit is set active when one
of the other bits in this register is the source of an interrupt event. All these error conditions are
caused by transitory events, therefore the error condition is latched (marked with an ‘L’).
Reading this status register causes all latched bits to be set inactive, unless an error event is
currently pending.
Setting any bit of this register High will cause an interrupt to be generated (N_IRQ will be set
Low) if the source of the interrupt has not been masked in the corresponding Mask register.
Name
0
0
Address field [6:0]
High
High
High
Data
High
High
High
Active State
0
Address and Data format for TxErrorStatus access
1
R
RL
RL
RL
R
RL
RL
RL
1
1
Reserved. Bit value is not defined.
Data path gain, phase and offset (GPO) adjustment-unit:
Q channel overflow error status bit.
Data path gain, phase and offset (GPO) adjustment-unit:
I channel overflow error status bit.
The Rx path decimation filter accumulator overflow error
status bit. (Note: For optimisation of the chip design, this
Rx control bit is located in a Tx control register)
Direct access to internal symbol clock enable signal. Allows
this timing reference to appear on the IRQ pin when
unmasked in the TxErrStatMask Register
63-tap I and Q Tx filter data accumulator overflow error
status bit.
79-tap I and Q Tx filter data accumulator overflow error
status bit.
This bit is set High if there is an active interrupt caused by
one of the status bits in this register.
0
47
R
D6 D5 D4 D3 D2
Data field [6:0]
Function
D1 D0
CMX980A
D/980A/3