CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 56

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
Title:
Address:
Function:
Description:
7:0
7:4
3:0
7:0
7:4
3:0
7:0
Bit
1999 Consumer Microcircuits Limited
TxRRCCoeffLSB
TxRRCCoeffMSB
Tx79tapCoeffLSB
Tx79tapCoeffMSB
RxRRCCoeffLSB
CoeffRamData
I/O access addresses for the four user-accessible coefficient memories.
$0x26 to $0x2D (mapped over 8 locations)
RW
Each coefficient RAM has both MSB and LSB address ports assigned for read/write access.
There are two transmit (Tx) FIR filters with read/write coefficients and two receive (Rx) filters,
with coefficient sizes of 12 and 16 bits respectively. Access to the coefficient memory is valid
only when the CoeffRamIoEn bit is active.
The MSB port should be accessed first, as accessing the LSB port will move the Coefficient
Address Pointer to the next coefficient location (A[n+1])
CoeffRamIoRdInc bit for details). Subsequent accesses to the LSB port of the coefficient
address will increment the Coefficient Address Pointer.
In the 79-tap Tx filter the coefficients are symmetrical and “odd” and only 40 locations can be
programmed. Performing an I/O access after the last Coefficient Address Pointer
( A[41-79] ) is not valid, and may corrupt existing coefficients.
All other filters have access to coefficients A1 to A[FirLength], thus the user can chose to
programme symmetrical or non-symmetrical filter responses. In either type of filter access to
the coefficient location A(FirLength+1) should be avoided as this location must contain zero for
correct filter operation.
Only one FIR filter coefficient RAM may be accessed at a time. If further filter coefficient RAMs
are to be accessed then the CoeffRamIoEn must first be deactivated, and then activated again,
allowing the next FIR filter coefficient RAM to be incrementally accessed.
Name
Asserting the CoeffRamIoEn will reset the Coefficient Address Pointer to the first location (A1).
Address $0x2A
Address $0x26
Address $0x27
Address $0x28
Address $0x29
Data
Data
Data
Data
Data
Active State
RW
RW
RW
RW
RW
RW
RW
Transmit 63-tap RRC filter LSB coefficient data port
Post-increment the coefficient address pointer.
Reserved. Set these bits High. Undefined on read.
Transmit 63-tap RRC filter MSB coefficient data port.
Transmit 79-tap filter LSB coefficient data port.
Post-increment the coefficient address pointer.
Reserved. Set these bits High. Undefined on read.
Transmit 79-tap filter MSB coefficient data port.
Receive 63-tap RRC filter LSB coefficient data port.
Post-increment the coefficient address pointer.
56
Function
(refer to description of
CMX980A
D/980A/3