CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 90

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
1.6.8
1.6.8.1 Auxiliary Section
1.6.8.2 Tx Section
1.6.8.3 Rx Section
1.6.8.4 Tx and Rx Bias Section
1999 Consumer Microcircuits Limited
Guidelines for use of Power Save Modes
The CMX980A contains a number of power save modes. In order to maximise flexibility for different
architectures and modes of operation, several register bits are available which control different parts of
the device. Operation of the various control bits are described in the appropriate sections. These
guidelines provide an overview of the power saving features.
When one or more Auxiliary DACs are not required, they can be individually powered down using the
PowerDownCtrl Register, bits [4:1]
When the auxiliary ADC channels are not required, the ADC will automatically power down if no ADC
channel is selected. If ADC conversions are only required occasionally, these can be performed in
single shot mode - the ADC will automatically power down between conversions.
When neither auxiliary ADC channels nor the RamDac function are required, the auxiliary section
digital logic can be powered down using the Aux_ClkStopMode bit in the ClkStopCtrl Register.
Note that the auxiliary ADC will power up within four master clock cycles, while the DAC circuits will
power up in less than 5µs.
The Tx can be powered down by setting TxEn and TxCtrlEn bits inactive and the TxClkStop bit active.
All of these bits are found in the TxSetup register. Note that TxEn should not be set inactive until the
TxPathEn bit in the TxFIFOStatus Register becomes inactive.
The power up time for the Tx is limited by the filter response time. Thus the analogue circuitry will be
correctly biased to receive data by the time the data emerges from the digital filters.
The Rx can be powered down by setting the RxEn bit in the RxSetup1 Register inactive and by
setting the RxClkStop and RxIFClkStopMode bits in the ClkStopCtrl Register active.
In addition, if the Rx AAF is not required, it is powered down using the RxAafPowDn bit in the
PowerDownCtrl Register. This bit also serves as a multiplex select for the function.
All of the analogue circuitry within the Rx will power up within 10µs. Thus, the time from power up to
valid data appearing at the RxDat pin will be dominated by the digital filter group delay (nominally 8
symbol periods).
When neither Tx nor Rx is required, the bias section can be powered down by setting the BiasPowDn
bit in the PowerDownCtrl Register inactive. A small amount of current can also be saved by setting
the BiasChainPowDn bit in the PowerDownCtrl Register inactive. However, this causes the voltage
on BIAS1 pin, which is used as the internal "analogue ground", to move towards V
time constant. Up to 2ms should be allowed for this node to recover before the Tx or Rx is enabled.
90
DD
with a 250µs
CMX980A
D/980A/3