S2067 AMCC (Applied Micro Circuits Corp), S2067 Datasheet - Page 7

• Manufacturer Part Number: S2067
• Description: Dual Serial Backplane Device With Dual I/o
• Manufacturer: AMCC (Applied Micro Circuits Corp)

The S2067 supports full and 1/2 rate operation for all
modes of operation. When RATE is LOW, the S2067
serial data rate equals the VCO frequency. When
RATE is HIGH, the VCO is divided by 2 before being
provided to the chip. Thus, the S2067 can support
Fibre Channel and serial backplane functions at both
full and 1/2 the VCO rate.
8B/10B Coding
The S2067 provides 8B/10B line coding for each
channel. The 8B/10B transmission code includes se-
rial encoding and decoding rules, special characters,
and error control. Information is encoded, 8 bits at a
time, into a 10-bit transmission character. The char-
acters defined by this code ensure that short run
lengths and enough transitions are present in the
serial bit stream to make clock recovery possible at
the receiver. The encoding also greatly increases
the likelihood of detecting any single or multiple er-
rors that might occur during the transmission and
reception of data
The 8B/10B transmission code includes D-charac-
ters, used for data transmission, and K-characters,
used for control or protocol functions. Each D-char-
acter and K-character has a positive and a negative
parity version. The parity of each codeword is se-
lected by the encoder to control the running disparity
of the data stream. K-character generation is con-
trolled individually for each channel using the
KGENx input. When KGEN is asserted, the data on
the parallel input is mapped into the corresponding
control character. The parity of the K-character is
selected to minimize running disparity in the serial
data stream. Table 2 lists the K characters sup-
Figure 6. DIN Data Clocking with TCLK
June 22, 2000 / Revision C
DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O
ASIC
MAC
1
.
TCLKO
DINx[0:7]
TCLKx
VC0/10 or VC0/20
OSCILLATOR
REFCLK
S2067
REF
PLL
ported by the S2067 and identifies the mapping of
the DIN[7:0] bits to each character.
A special input is provided to simplify the generation
of the K28.5 character. An SOFx input is provided
for each channel. When SOF is asserted, the K28.5
character is generated regardless of the data on the
parallel input. The K28.5 character can be of either
positive or negative parity, depending on the current
running disparity. Table 3 shows the mapping of the
8B/10B characters representation. Data is transmit-
ted bit “a” or DIN[0] first.
In addition to data and K characters, the S2067 can
also generate a unique sync sequence consisting of
16 consecutive K28.5 characters. This event is initi-
ated by the simultaneous assertion of KGENx and
SOFx for one clock period. The SOFx and KGENx
inputs should be held low until the sync sequence
has completed. The sync sequence may start with
either a positive or negative parity K28.5. (Depend-
ing on the current running disparity.) The parity of
the second and third K28.5 are inverse with respect
to a valid 8B/10B sequence. Parity of the remaining
K28.5 alternate in accordance with the 8B/10B cod-
ing standard. Thus, the parity of the K28.5 pattern
consists of + + - - + - + - + - + - + - + - or - - + + - + -
+ - + - + - + - +. Table 4 shows the transmitter control
signals.
1
Figure 7. DIN Clocking with REFCLK
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC9391, May 1982.
A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-
ASIC
MAC
TCLKO
DINx[0:7]
TCLKx
OSCILLATOR
REFCLK
S2067
VC0/10
REF
PLL
S2067
7