AD9215-65 Analog Devices, AD9215-65 Datasheet - Page 10

• Manufacturer Part Number: AD9215-65
• Description: 10-Bit, 65/80/105 MSPS 3.3 V A/D Converter
• Manufacturer: Analog Devices

AD9215
External
SENSE
Connection
AVDD
VREF
External Divider Noninverting (1 < G < 2) Programmed Variable Reference
AGND to 0.2 V
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 11, the power dissipated by the AD9215 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades,
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as:
where N is the number of output bits, 10 in the case of the
AD9215. This maximum current is for the condition of every
output bit switching on every clock cycle, which can only occur
for a full scale square wave at the Nyquist frequency, f
In practice, the DRVDD current will be established by the average
number of output bits switching, which will be determined by
the encode rate and the characteristics of the analog input signal.
Code
1023
512
511
0
Figure 11. Total Power vs. Sample Rate with f
325
300
275
250
225
200
175
150
125
100
75
50
0
I
AD9215–60
DRVDD
10
VIN+ – VIN–
Input Span = 2Vp-p
(V)
1.000
0
–0.00195
–1.00
Internal
Op Amp
Configuration
N/A
Voltage Follower (G = 1)
Internal Divider
= V
AD9215–80
DRVDD
20
SAMPLE RATE – MSPS
AD9215–105
× C
30
PRELIMINARY TECHNICAL DATA
LOAD
40
× f
CLOCK
50
Table II. AD9215 Digital Output Coding
VIN+ – VIN–
Input Span = 1Vp-p
(V)
0.500
0
–0.000978
–0.5000
Table I. Reference SENSE Operation
Selected
Mode
Externally Supplied Reference
Internal 0.5 V Reference
Internally Programmed 1 V Reference 1.0
× N
60
IN
= 10 MHz
CLOCK
0
/2.
–10–
Digital power consumption can be minimized by reducing the
capacitive load presented to the output drivers. The data in
Figure 11 was taken with a TBD pF load on each output driver.
The analog circuitry is optimally biased so that each speed grade
provides excellent performance while affording reduced power
consumption. Each speed grade dissipates a baseline power at
low sample rates that increases linearly with the clock frequency.
By asserting the PDWN pin high, the AD9215 is placed in
standby mode. In this state the A/D will typically dissipate 1 mW if
the CLOCK and analog inputs are static. During standby the
output drivers are placed in a high impedance state. Reasserting
the PDWN pin low returns the AD9215 into its normal opera-
tional mode.
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode, and then must be recharged when return-
ing to normal operation. As a result, the wake-up time is related
to the time spent in standby mode, and shorter standby cycles
will result in proportionally shorter wake-up times. With the
recommended 0.1 µF and 10 µF decoupling capacitors on REFT
and REFB, it takes approximately one second to fully dis-
charge the reference buffer decoupling capacitors, and 5 ms to
restore full operation.
DIGITAL OUTPUTS
The AD9215 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
As detailed in Table III, the data format can be selected for
either offset binary or two’s complement.
Digital Output
Offset Binary
(D9••••••D0)
11 1111 1111
10 0000 0000
01 1111 1111
00 0000 0000
Resulting
VREF (V)
N/A
0.5
0.5
(1 + R2/R1) 2
11 1111 1111
10 0000 0000
Digital Output
Two’s Compliment
(D9••••••D0)
01 1111 1111
00 0000 0000
Resulting
Differential
Span (V p-p)
2 × External Reference
1.0
2.0
VREF
REV. PrA