MAX11645 Maxim Integrated Products, MAX11645 Datasheet - Page 11

• Manufacturer Part Number: MAX11645
• Description: 2-Wire Serial 12-Bit ADCs
• Manufacturer: Maxim Integrated Products

Internal protection diodes clamp the analog input to V
and GND. These diodes allow the analog inputs to swing
from (GND - 0.3V) to (V
age to the device. For accurate conversions, the inputs
must not go more than 50mV below GND or above V
The SGL/DIF of the configuration byte configures the
MAX11644/MAX11645 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are
the difference between the analog input selected by
CS[0] and GND (Table 3). In differential mode (SGL/
DIF = 0), the digital conversion results are the differ-
ence between the + and the - analog inputs selected
by CS[0] (Table 4).
When operating in differential mode, the BIP/UNI bit of
the set-up byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to V
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to ±V
ry in unipolar mode and two’s complement in bipolar
mode. See the Transfer Functions section.
In single-ended mode, the MAX11644/MAX11645
always operate in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to V
The MAX11644/MAX11645 feature a 2-wire interface
consisting of a serial-data line (SDA) and serial-clock
line (SCL). SDA and SCL facilitate bidirectional commu-
nication between the MAX11644/MAX11645 and the
master at rates up to 1.7MHz. The MAX11644/
MAX11645 are slaves that transfer and receive data.
The master (typically a microcontroller) initiates data
transfer on the bus and generates the SCL signal to
permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ω or greater) (see the Typical
Operating Circuit ). Series resistors (RS) are optional. They
protect the input architecture of the MAX11644/
MAX11645 from high voltage spikes on the bus lines and
minimize crosstalk and undershoot of the bus signals.
One data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX11644/MAX11645.
Analog Input Range and Protection
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
Single-Ended/Differential Input
REF
______________________________________________________________________________________
REF
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
/2. The digital output code is bina-
. A negative differential analog
DD
2-Wire Digital Interface
+ 0.3V) without causing dam-
Unipolar/Bipolar
Bit Transfer
REF
.
DD
DD
.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
The master initiates a transmission with a START (S)
condition, a high-to-low transition on SDA while SCL is
high. The master terminates a transmission with a STOP
(P) condition, a low-to-high transition on SDA while SCL
is high (Figure 5). A repeated START (Sr) condition
can be used in place of a STOP condition to leave the
bus active and the interface mode unchanged (see the
HS Mode section).
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX11644/MAX11645 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 6). To generate a not-acknowledge,
the receiver allows SDA to be pulled high before the
rising edge of the acknowledge-related clock pulse
and leaves SDA high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer happens if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
Figure 5. START and STOP Conditions
Figure 6. Acknowledge Bits
SDA
SCL
SDA
SCL
S
S
1
START and STOP Conditions
2
Sr
NOT-ACKNOWLEDGE
Acknowledge Bits
ACKNOWLEDGE
w w w . D a t a S h e e t 4 U .
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P
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