HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 24

• Manufacturer Part Number: HFC-Smini
• Manufacturer: Cologne Chip AG

863 C ]Y^Y
[R1]
[R2]
[R3]
[R4]
In Simple Mode (SM) the CHANNEL number is the same as the FIFO number. If Channel Select
Mode (CSM) is enabled the transmit CHANNEL for a FIFO can be selected by
Please note that receive CHANNELs are odd numbered (bit 0 of CHANNEL# register = '1').
The bit values of the not processed bits of the receive CHANNEL are ignored. The processed
bits are taken from the CHANNEL (see also: Subchannel Processing). Please note that more than
one FIFO can receive data from the same CHANNEL (e.g. bits 1..0 are processed by FIFO 1 and
bits 3..2 by FIFO 3). This is useful to split subchannels that have been combined to be
transmitted in one ISDN channel.
Data can either be received from the S/T interface or the PCM interface.
The CON_HDLC register bits 7..5 settings must be the same for corresponding receive and
transmit FIFOs.
A PCM SLOT can be connected to a CHANNEL.
The PCM SLOT number for a FIFO can be selected by writing the desired SLOT number to its
timeslot selection register shown in the table above. Please note that only the *_RSL registers are
for receive slots.
(FIFO#, bits 2..0)
FIFO-No.
1) writing the FIFO number (0..7) in the FIFO# register
2) writing the desired CHANNEL number (0..7) to the CHANNEL# register (bits 2..0)
1) write the FIFO number (0..7) in the FIFO# register
2) write the desired connection to the CON_HDLC register bits 7..5
'000'
'001'
'010'
'011'
'100'
'101'
'110'
'111'
B1_SSL
B1_RSL
B2_SSL
B2_RSL
AUX1_SSL
AUX1_RSL
AUX2_SSL
AUX2_RSL
Register for
Selection
Timeslot
Cologne
Chip