HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 5

• Manufacturer Part Number: HFC-Smini
• Manufacturer: Cologne Chip AG

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Figures
Figure 1: HFC-S mini block diagram............................................................................................................ 7
Figure 2: Pin Connection .............................................................................................................................. 9
Figure 3: FIFO Organisation....................................................................................................................... 14
Figure 4: FIFO Data Organisation .............................................................................................................. 16
Figure 5: FIFOs, CHANNELs and SLOTs in Transmit Direction ............................................................. 22
Figure 6: FIFOs, CHANNELs and SLOTs in Receive Direction............................................................... 23
Figure 7: Example for Subchannel Processing ........................................................................................... 25
Figure 8: PCM Interface Function Block Diagram..................................................................................... 26
Figure 9: Function of CON_HDLC register bits 7..5 ................................................................................. 37
Figure 10: External receiver circuitry......................................................................................................... 59
Figure 11: External wake-up circuitry ........................................................................................................ 60
Figure 12: External transmitter circuitry .................................................................................................... 61
Figure 13: Oscillator circuitry for S/T clock .............................................................................................. 64
Figure 14: Frame structure at reference point S and T ............................................................................... 67
Figure 15: Single channel GCI format........................................................................................................ 68
Figure 16: Clock synchronisation in NT-mode .......................................................................................... 69
Figure 17: Clock synchronisation in TE-mode ........................................................................................... 70
Figure 18: Multiple HFC-S mini SYNC scheme ........................................................................................ 71
Figure 19: HFC-S mini package dimensions .............................................................................................. 72
Tables
Table 1: Function of the microprocessor interface control signals ............................................................ 12
Table 2: Possible connections of FIFOs and CHANNELs in Simple Mode (SM)..................................... 20
Table 3: CHANNEL Numbers on the S/T Interface and PCM Interface ................................................... 21
Table 4: S/T module part numbers and manufacturers............................................................................... 63
Table 5: Activation/deactivation layer 1 for finite state matrix for NT ..................................................... 65
Table 6: Activation/deactivation layer 1 for finite state matrix for TE...................................................... 66
Timing diagrams
Timing diagram 1: Register read access in de-multiplexed Motorola mode (mode 2) .............................. 50
Timing diagram 2: Register write access in de-multiplexed Motorola mode (mode 2) ............................. 51
Timing diagram 3: Register read access in de-multiplexed Intel mode (mode 3) ...................................... 52
Timing diagram 4: Register write access in de-multiplexed Intel mode (mode 3)..................................... 53
Timing diagram 5: Register read access in multiplexed mode (mode 4) ................................................... 54
Timing diagram 6: Register write access in multiplexed mode (mode 4) .................................................. 55
Timing diagram 7: PCM/GCI/IOM2 timing ............................................................................................... 56
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