HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 44

• Manufacturer Part Number: HFC-Smini
• Manufacturer: Cologne Chip AG

863 C ]Y^Y
Name
SCTRL
SCTRL_E
Addr.
31h
32h
Bits
6..5
1
2
3
4
5
6
7
0
1
2
3
4
7
0
r/w Function
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
'0' B1 send data disabled (permanent 1 sent in activated states,
'1' B1 data enabled
'0' B2 send data disabled (permanent 1 sent in activated states,
'1' B2 data enabled
S/T interface mode
'0' TE mode (reset default)
'1' NT mode
D-channel priority
'0' high priority 8/9 (reset default)
'1' low priority 10/11
S/Q bit transmission
'0' S/Q bit disable (reset default)
'1' S/Q bit and multiframe enable
'0' normal operation (reset default)
'1' send 96kHz transmit test signal (alternating zeros)
TX_LO line setup
This bit must be configured depending on the used S/T module
and circuitry to match the 400 pulse mask test.
'0' capacitive line mode (reset default)
'1' non capacitive line mode
Power down
'0' power up, oscillator active (reset default)
'1' power down, oscillator stopped
Oscillator is restarted when AWAKE input becomes '1' or on
any write access to the HFC-S mini.
force G2
automatic transition from G2
STATES register
must be '0'
D reset
'0' normal operation (reset default)
'1' D bits are forced to '1'
D_U enable
'0' normal operation (reset default)
'1' D channel is always send enabled regardless of E receive
force E='0' (NT mode)
'0' normal operation (reset default)
'1' E-bit send is forced to '0'
must be '0'
'1' swap B1 and B2-channel in the S/T interface
reset default)
reset default)
bit
G3
G3 without setting bit 7 of
Cologne
Chip