WM8594_07 Wolfson Microelectronics Ltd., WM8594_07 Datasheet - Page 21

• Manufacturer Part Number: WM8594_07
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics Ltd.

Product Preview
GLOBAL ENABLE CONTROL
DIGITAL AUDIO INTERFACE
w
DEVICE ID AND REVISION
Reading from register R0 returns the device ID. Reading from register R1 returns the device revision
number.
The WM8594 includes a number of enable and disable mechanisms to allow the device to be
powered on and off in a pop-free manner. A global enable control bit enables the ADC, DAC and
analogue paths. For full details of pop-free operation, see ‘Pop and Click Performance’ on page 44.
Digital audio data is transferred to and from the WM8594 via the digital audio interface. The DACs
have independent data inputs and master clocks, bit clocks and left/right frame clocks, and operate
in both master or slave mode The ADC has independent master clock, bit clock and left/right frame
clock in addition to its data output, and can operate in both master and slave modes.
MASTER MODE
The ADC audio interface requires both a left/right frame clock (ADCLRCLK) and a bit clock
(ADCBCLK). These can be supplied externally (slave mode) or they can be generated internally
(master mode). Selection of master and slave mode is achieved by setting ADC_MSTR in ADC
Control Register 15.
The frequency of ADCLRCLK in master mode is dependent upon the ADC master clock frequency
and the ADC_SR[2:0] bits.
The frequency of ADCBCLK in master mode can be selected by ADC_BCLKDIV[1:0].
The DAC audio interfaces require both left/right frame clocks (DACLRCLK1, DACLRCLK2) and bit
clocks (DACBCLK1, DACBCLK2). These can be supplied externally (slave mode) or they can be
generated internally (master mode). Selection of master and slave mode is achieved by setting
DAC1_MSTR in DAC1 Control Register 4 and DAC2_MSTR in DAC2 Control Register 9.
The frequency of DACLRCLK1 in master mode is dependent upon the DAC1 master clock frequency
and the DAC1_SR[2:0] bits. Similarly the frequency of DACLRCLK2 in master mode is dependent
upon the DAC2 master clock frequency and the DAC2_SR[2:0] bits.
The frequency of DACBCLK1 and DACBCLK2 in master mode can be selected by
DAC1_BCLKDIV[1:0] and DAC2_BCLKDIV[1:0].
Table 9 Device ID and Revision Number
Table 10 Global Enable Control
DEVICE_ID
REGISTER
REGISTER
ADDRESS
ADDRESS
REVISION
ENABLE
R12
0Ch
00h
01h
R0
R1
15:0
BIT
BIT
7:0
0
DEVICE_ID
GLOBAL_
REVNUM
LABEL
LABEL
[15:0]
[7:0]
EN
DEFAULT
DEFAULT
10000101
10010100
N/A
0
Device ID
A read of this register will return the device
ID, 0x8594.
Device Revision
A read of this register will return the device
revision number. This number is sequentially
incremented if the device design is updated.
Device Global Enable
0 = ADC, DAC and PGA ramp control
circuitry disabled
1 = ADC, DAC and PGA ramp control
circuitry enabled
DESCRIPTION
DESCRIPTION
PP Rev 1.0 January 2007
WM8594
21