WM8594_07 Wolfson Microelectronics Ltd., WM8594_07 Datasheet - Page 25

• Manufacturer Part Number: WM8594_07
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics Ltd.

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DIGITAL AUDIO DATA FORMATS
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The WM8594 supports a range of common audio interface formats:
I2S MODE
In I
left/right clock transition. The MSB of output data changes on the first falling edge of bit clock
following a left/right clock transition, and may be sampled on the next rising edge of bit clock.
Left/right clocks are low during the left channel audio data samples and high during the right channel
audio data samples.
Figure 12 I2S Mode Timing
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All formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception
of 32 bit RJ mode, which is not supported.
Audio data for each stereo channel is time multiplexed with the interface’s left/right clock indicating
whether the left or right channel is present. The left/right clock is also used as a timing reference to
indicate the beginning or end of the data words.
In LJ, RJ and I
times the selected word length. The left/right clock must be high for a minimum of bit clock periods
equivalent to the word length, and low for the same period. For example, for a word length of 24 bits,
the left/right clock must be high for a minimum of 24 bit clock periods and low for a minimum of 24
bit clock periods. Any mark to space ratio is acceptable for the left/right clock provided these
requirements are met.
In DSP modes A and B, left and right channels must be time multiplexed and input on DIN1. LRCLK
is used as a frame synchronisation signal to identify the MSB of the first input word. The minimum
number of bit clock periods per left/right clock period is two times the selected word length. Any
mark to space ratio is acceptable for the left/right clock provided the rising edge is correctly
positioned.
2
S mode, the MSB of input data is sampled on the second rising edge of bit clock following a
I
Left Justified (LJ)
Right Justified (RJ)
DSP Mode A
DSP Mode B
2
S
2
S modes, the minimum number of bit clock periods per left/right clock period is two
PP Rev 1.0 January 2007
WM8594
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