WM8594_07 Wolfson Microelectronics Ltd., WM8594_07 Datasheet - Page 69

• Manufacturer Part Number: WM8594_07
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics Ltd.

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R36 (24h) – PGA Control Register 3 (PGA_CTRL3)
Figure 50 R36 – PGA Control Register 3
R37 (25h) – ADC Input Clock Control Register (ADC_CLK)
Figure 51 R37 – ADC Input Clock Control Register
w
Default
Default
Default
Default
Write
Write
Write
Write
Read
Read
Read
Read
Bit #
Bit #
Bit #
Bit #
PGA_SAFE_SW
ADC_SAFE_SW
PGA_SEL[2:0]
PGA_UPD
Function
Function
N/A
N/A
N/A
N/A
15
15
0
7
0
0
7
0
0
0
0
0
PGA Ramp Control Clock Source Mux Force Update
0 = Wait until clocks are safe before switching PGA clock source
1 = Force PGA clock source to change immediately
See page 37 for details of use.
PGA Ramp Control Clock Source
000 = ADCLRCLK
001 = DACLRCLK1
010 = DACLRCLK2
011 = reserved
100 = reserved
101 = DACLRCLK1 (when DAC1 is being used in master mode)
110 = DACLRCLK2 (when DAC2 is being used in master mode)
111 = ADCLRCLK (when ADC is being used in master mode)
PGA Ramp Control Clock Source Mux Update
0 = Do not update PGA clock source
1 = Update clock source
ADC Clock Input Safe Switching
0 = Ignore ADC Clock Inputs
1 = Use ADC Clock Inputs
See page 33 for details of use
N/A
N/A
N/A
N/A
14
14
0
0
6
0
0
0
0
6
0
0
N/A
N/A
N/A
N/A
13
13
0
0
5
0
0
0
0
5
0
0
N/A
N/A
N/A
N/A
12
12
0
0
4
0
0
0
0
4
0
0
Description
Description
N/A
N/A
N/A
11
11
0
3
0
3
0
0
0
0
0
N/A = Not Applicable (no function implemented)
N/A = Not Applicable (no function implemented)
PGA_SEL[2:0]
PGA_UPD
N/A
N/A
10
10
0
2
0
0
0
2
0
0
PP Rev 1.0 January 2007
N/A
N/A
N/A
9
0
0
1
0
9
0
0
1
0
0
WM8594
SAFE_SW
SAFE_SW
PGA_
ADC_
N/A
N/A
8
0
0
0
0
8
0
0
0
0
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