WM8594_07 Wolfson Microelectronics Ltd., WM8594_07 Datasheet - Page 33

• Manufacturer Part Number: WM8594_07
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics Ltd.

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ANALOGUE ROUTING CONTROL
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HIGH PASS FILTER
The WM8594 includes a high pass filter to remove DC offsets. The high pass filter response is
shown on page 73. It is possible to disable the high pass filter by writing to ADC_HPD.
CLOCK SWITCHING
The input clocks to the ADC (ADCMCLK, ADCBCLK, ADCLRCLK) can be switched between sources
if the ADC is used to supply data to multiple DSPs or application processors. Uncontrolled switching
of clocks is not recommended as this may result in clock glitches being applied to the ADC.
The WM8594 can be configured to ignore the clock inputs so that the clocks can be switched
externally. This means that the WM8594 is not affected by any glitches that arise as a result of
switching clocks. The ADC should be configured to ignore the input clocks for the duration of the
period taken to switch the clocks.
The WM8594 has a number of analogue paths, allowing flexible routing of a number of analogue
input signals and DAC output signals at levels up to 2Vrms. The analogue paths include volume
control with zero cross, optional soft ramp and soft mute, and flexible routing of analogue inputs and
DAC outputs to analogue outputs.
Table 24 ADC Channel Swap Control
Table 25 High Pass Filter Disable Control
Table 26 ADC Clock Switching Control
ADC_CTRL1
ADC_CTRL1
REGISTER
REGISTER
REGISTER
ADDRESS
ADDRESS
ADDRESS
ADC_CLK
R13
0Dh
R13
0Dh
R37
25h
11:10
BIT
BIT
BIT
12
7
8
9
0
SAFE_SW
ADC_HPD
LRSWAP
SEL[1:0]
ADCR_
LABEL
LABEL
LABEL
ADCL_
DATA_
ADC_
ADC_
ADC_
INV
INV
DEFAULT
DEFAULT
DEFAULT
00
0
0
0
0
0
ADC Left/Right Swap
0 = Normal
1 = Swap left channel data into right channel
and vice-versa
ADCL and ADCR Output Signal Inversion
0 = Output not inverted
1 = Output inverted
ADC Data Output Select
00 = left data from ADCL, right data from
ADCR
01 = left data from ADCL, right data from
ADCL
10 = left data from ADCR, right data from
ADCR
11 = left data from ADCR, right data from
ADCL
ADC High Pass Filter Disable
0 = High pass filter enabled
1 = High pass filter disabled
ADC Clock Input Safe Switching
0 = Ignore ADC Clock Inputs
1 = Use ADC Clock Inputs
DESCRIPTION
DESCRIPTION
DESCRIPTION
PP Rev 1.0 January 2007
WM8594
33