WM8594_07 Wolfson Microelectronics Ltd., WM8594_07 Datasheet - Page 56

• Manufacturer Part Number: WM8594_07
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics Ltd.

WM8594
Figure 35 R13 – ADC Control Register 1
R14 (0Eh) – ADC Control Register 2 (ADC_CTRL2)
Figure 36 R14 – ADC Control Register 2
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Default
Default
ADC_DATA_SEL[1:0]
Write
Write
Read
Read
Bit #
Bit #
ADC_BCLKDIV[2:0]
ADC_LRSWAP
ADC_SR[2:0]
ADC_ZC_EN
ADCR_INV
ADCL_INV
ADC_HPD
Function
N/A
N/A
15
0
7
0
0
0
ADC Left/Right Swap
0 = Normal
1 = Swap left channel data into right channel and vice-versa
ADCL and ADCR Output Signal Inversion
0 = Output not inverted
1 = Output inverted
ADC Data Output Select
00 = left data from ADCL, right data from ADCR (Normal Stereo)
01 = left data from ADCL, right data from ADCL (Mono Left)
10 = left data from ADCR, right data from ADCR (Mono Right)
11 = left data from ADCR, right data from ADCL (Reverse Stereo)
ADC High Pass Filter Disable
0 = High pass filter enabled
1 = High pass filter disabled
ADC Digital Volume Control Zero Cross Enable
0 = Do not use zero cross, change volume instantly
1 = Use zero cross, change volume when data crosses zero
ADC MCLK:LRCLK Ratio
000 = Auto detect
001 = reserved
010 = reserved
011 = 256fs
100 = 384fs
101 = 512fs
110 = 768fs
111 = Reserved
ADC BCLK Rate (when ADC in Master Mode)
000 = MCLK / 4
001 = MCLK / 8
010 = 32fs
011 = 64fs
100 = 128fs
All other values of ADC_BCLKDIV[2:0] are reserved
N/A
N/A
14
0
0
6
0
0
N/A
13
0
0
5
0
ADC_BCLKDIV[2:0]
N/A
12
0
0
4
0
Description
N/A
11
0
3
0
0
N/A = Not Applicable (no function implemented)
N/A
10
0
0
2
0
ADC_SR[2:0]
PP Rev 1.0 January 2007
N/A
9
0
0
1
0
Product Preview
N/A
8
0
0
0
0
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