WM8978_06 Wolfson Microelectronics Ltd., WM8978_06 Datasheet - Page 15

• Manufacturer Part Number: WM8978_06
• Description: Stereo Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics Ltd.

Pre-Production
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 1 System Clock Timing Requirements
Note 1:
PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.
AUDIO INTERFACE TIMING – MASTER MODE
w
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T
PARAMETER
System Clock Timing Information
MCLK cycle time
MCLK duty cycle
MCLK
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
SYMBOL
T
T
MCLKDS
MCLKY
t
MCLKL
t
MCLKY
MCLK=SYSCLK (=256fs)
MCLK input to PLL
t
MCLKH
CONDITIONS
Note 1
A
= +25
81.38
60:40
MIN
20
o
C
TYP
PP Rev 3.0 May 2006
40:60
MAX
WM8978
UNIT
ns
ns
15