WM8978_06 Wolfson Microelectronics Ltd., WM8978_06 Datasheet - Page 79

• Manufacturer Part Number: WM8978_06
• Description: Stereo Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics Ltd.

Pre-Production
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Table 57 Clock Control
R6
Clock
Generation
Control
REGISTER
ADDRESS
0
4:2
7:5
8
BIT
MS
BCLKDIV
MCLKDIV
CLKSEL
LABEL
0
000
010
1
DEFAULT
Sets the chip to be master over LRC
and BCLK
0=BCLK and LRC clock are inputs
1=BCLK and LRC clock are outputs
generated by the WM8978 (MASTER)
Configures the BCLK output frequency,
for use when the chip is master over
BCLK.
000=divide by 1 (BCLK=SYSCLK)
001=divide by 2 (BCLK=SYSCLK)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
Sets the scaling for either the MCLK or
PLL clock output (under control of
CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
Controls the source of the clock for all
internal operation:
0=MCLK
1=PLL output
DESCRIPTION
PP Rev 3.0 May 2006
WM8978
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