WM8978_06 Wolfson Microelectronics Ltd., WM8978_06 Datasheet - Page 22

• Manufacturer Part Number: WM8978_06
• Description: Stereo Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics Ltd.

WM8978
Figure 9 ADC Power Up and Down Sequence (not to scale)
w
BIASEN bits
Power Supply
POR
I
ADC Internal
Analogue Inputs
ADCDAT pin
ADCEN bit
(Note 3)
INPPGAEN bit
2
VMIDSEL/
S Clocks
State
(Note 4)
V
pora
POR Undefined
No Power
V
por_on
Power down
AVDD/2
DGND
Table 4 Typical POR Operation (typical simulated values)
ADC Group Delay
Notes:
1.
2.
3.
In addition to the power on sequence, it is recommended that the zero cross functions are used
when changing the volume in the PGAs to avoid any audible pops or clicks.
(Note 1)
SYMBOL
t
t
This step enables the internal device bias buffer and the VMID buffer for unassigned
inputs/outputs. This will provide a startup reference voltage for all inputs and outputs. This will
cause the inputs and outputs to ramp towards VMID (NOT using output 1.5x boost) or 1.5 x
(AVDD/2) (using output 1.5x boost) in a way that is controlled and predictable (see note 2).
Choose the value of the VMIDSEL bits based on the startup time (VMIDSEL=10 for slowest
startup, VMIDSEL=11 for fastest startup). Startup time is defined by the value of the VMIDSEL
bits (the reference impedance) and the external decoupling capacitor on VMID.
Setting DACEN to off while operating in x1.5 boost mode will cause the VMID voltage to drop to
AVDD/2 midrail level and cause an output pop.
POR
midrail_on
midrail_off
t
adcint
t
midrail_on
DNC
Init
t
adcint
GD
MIN
Normal Operation
ADC enabled
TYPICAL
29/fs
500
>10
2/fs
GD
INPPGA enabled
Device Ready
VMID enabled
ADC off
DNC
PD
MAX
Init
GD
t
adcint
UNIT
n/fs
n/fs
ms
s
ADC enabled
Normal Operation
GD
t
midrail_off
Internal POR active
Power down
PP Rev 3.0 May 2006
(Note 2)
V
Pre-Production
por_off
22