WM8978_06 Wolfson Microelectronics Ltd., WM8978_06 Datasheet - Page 23
WM8978_06
Manufacturer Part Number
WM8978_06
Description
Stereo Codec With Speaker Driver
Manufacturer
Wolfson Microelectronics Ltd.
Datasheet
1.WM8978_06.pdf
(119 pages)
- Current page: 23 of 119
- Download datasheet (2Mb)
Pre-Production
Figure 10 DAC Power Up and Down Sequence (not to scale)
w
1.
2.
3.
4.
5.
6.
Notes:
The analogue input pin charge time, t
time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance
and AVDD power supply rise time.
The analogue input pin discharge time, t
capacitor discharge time. The time, t
analogue input but will vary dependent upon the value of input coupling capacitor.
While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system
noise but no significant digital output will be present.
The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for
normal ADC operation.
ADCDAT data output delay from power up - with power supplies starting from 0V - is determined
primarily by the VMID charge time. ADC initialisation and power management bits may be set
immediately after POR is released; VMID charge time will be significantly longer and will dictate
when the device is stabilised for analogue input.
ADCDAT data output delay at power up from device standby (power supplies already applied) is
determined by ADC initialisation time, 2/fs.
midrail_on,
midrail_off
midrail_off,
is determined by the VMID pin charge time. This
, is measured using a 1µF capacitor on the
is determined by the analogue input coupling
PP Rev 3.0 May 2006
WM8978
23
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