ADA4410-6 Analog Devices, ADA4410-6 Datasheet - Page 13

• Manufacturer Part Number: ADA4410-6
• Manufacturer: Analog Devices

APPLICATIONS
OVERVIEW
With its high impedance multiplexed inputs and high output
drive, the ADA4410-6 is ideally suited to video reconstruction
and antialias filtering applications. The high impedance inputs
give designers flexibility with regard to how the input signals
are terminated. Devices with DAC outputs that feed the
ADA4410-6 can be loaded in whatever resistance provides
the best performance, and devices with voltage outputs can be
optimally terminated as well. The ADA4410-6 outputs can each
drive up to two source-terminated 75 Ω loads and can therefore
directly drive the outputs from set-top boxes, DVD players, and
the like without the need for a separate output buffer.
Binary control inputs are provided to select cutoff frequency,
throughput gain, and input signal. These inputs are compatible
with 3 V and 5 V TTL and CMOS logic levels, referenced to
GND. The disable feature is asserted by pulling the DISABLE
pin to the positive supply.
A differential input, comprising of the LEVEL1 and LEVEL2
inputs, controls the dc level at the output pins. The output offset
is nominally calculated as
where LEVEL2 and LEVEL1 are the voltages applied to the
respective inputs and G is throughput gain.
MULTIPLEXER SELECT INPUTS
Selection between the two multiplexer inputs is controlled by
the logic signals applied to the MUX_SD and MUX_HD inputs.
The MUX_SD input controls the standard definition (SD)
inputs, and the MUX_HD input controls the high definition
(HD) inputs. Table 6 summarizes the multiplexer operation.
GAIN SELECT
The throughput gain of the ADA4410-6 signal paths can
either be ×2 or ×4. Gain selection is controlled by the logic
signal applied to the G_SEL pin. Table 6 summarizes how the
gain is selected.
DISABLE
The ADA4410-6 includes a disable feature that can be used
to save power when a particular device is not in use. As
indicated in the Overview section, the disable feature is
asserted by pulling the DISABLE pin to the positive supply.
Table 6 summarizes the disable feature operation. The
DISABLE pin also functions as a reference level for the logic
inputs and, therefore, must be connected to ground when the
device is not disabled.
V
OS
(
OUT
)
=
(
LEVEL2
−
LEVEL1
)(
G
)
Rev. 0 | Page 13 of 16
(1)
Table 6. Logic Pin Function Description
DISABLE
V
Disabled
GND =
Enabled
CUTOFF FREQUENCY SELECTION
Four combinations of cutoff frequencies are provided for the
HD video signals. The cutoff frequencies have been selected to
correspond with the most commonly deployed HD scanning
systems. Selection between the cutoff frequency combinations is
controlled by the logic signals applied to the F_SEL_A and
F_SEL_B inputs. Table 7 summarizes cutoff frequency selection.
Table 7. Filter Cutoff Frequency Selection
F_SEL_A
0
0
1
1
OUTPUT DC OFFSET CONTROL
The LEVEL1 and LEVEL2 inputs work as a differential
input-referred output offset control. In other words, the output
offset voltage of a given channel (with the exception of the CV
channel) is equal to the difference in voltage between the
LEVEL2 and LEVEL1 inputs, multiplied by the overall filter
gain. This relationship is expressed in Equation 1. For example,
with the G_SEL input set for ×2 gain, setting LEVEL2 to
300 mV and LEVEL1 to 0 V shifts the offset voltages at the
ADA4401-6 outputs to 600 mV. This particular setting can be
used in most single-supply applications to keep the output
swings safely above the negative supply rail.
The CV output is developed by passively summing the Y and C
outputs that have passed through their respective output gain
stages, then multiplying this sum by a factor of two to obtain
the output (see Figure 1). The offset of this output is therefore
equal to two times that of the other outputs. Because of this, in
many cases it is necessary to ac-couple the CV output or ensure
that it is connected to an input that is ac-coupled. This is
generally not an issue because it is common practice to employ
ac coupling on composite video inputs.
The maximum differential voltage that can be applied across the
LEVEL1 and LEVEL2 inputs is ±500 mV. From a single-ended
standpoint, the LEVEL1 and LEVEL2 inputs have the same
range as the filter inputs. See the Specifications tables for the
limits. The LEVEL1 and LEVEL2 inputs must each be bypassed
to GND with a 0.1 µF ceramic capacitor.
S+
=
F_SEL_B
0
1
0
1
MUX_HD
1 = HD Channel 1
Selected
0 = HD Channel 2
Selected
Y/G Cutoff
(MHz)
36
36
18
9
MUX_SD
1 = SD Channel 1
Selected
0 = SD Channel 2
Selected
Pb/B Cutoff
(MHz)
36
18
18
9
ADA4410-6
Pr/R Cutoff
(MHz)
36
18
18
9
G_SEL
1 = ×4
Gain
0 = ×2
Gain