MCIMX31 Motorola Semiconductor Products, MCIMX31 Datasheet - Page 69

• Manufacturer Part Number: MCIMX31
• Manufacturer: Motorola Semiconductor Products

Display read operation can be performed with wait states when each read access takes up to 4 display
interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the
DI_DISP0_TIME_CONF_3, DI_DISP1_TIME_CONF_3, DI_DISP2_TIME_CONF_3 Registers.
Figure 55
Freescale Semiconductor
DISPB_PAR_RS
DISPB_PAR_RS
DISPB_PAR_RS
DISPB_D#_CS
DISPB_D#_CS
DISPB_WR
(READ/WRITE)
DISPB_D#_CS
DISPB_WR
(READ/WRITE)
DISPB_WR
(READ/WRITE)
DISPB_BCLK
DISPB_DATA
DISPB_DATA
DISPB_DATA
DISPB_RD
(ENABLE)
DISPB_RD
(ENABLE)
DISPB_RD
(ENABLE)
Figure 54. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram
shows timing of the parallel interface with read wait states.
Single access mode (all control signals are not active for one display interface clock after each display access)
Burst access mode with sampling by separate burst clock (BCLK)
MCIMX31/MCIMX31L Advance Information, Rev. 3.2
Preliminary—Subject to Change Without Notice
Burst access mode with sampling by ENABLE signal
Electrical Characteristics
69