AD1821 Analog Devices, AD1821 Datasheet - Page 14

• Manufacturer Part Number: AD1821
• Manufacturer: Analog Devices

AD1821
HOST INTERFACE
The AD1821 contains all necessary ISA bus interface logic on-
chip. This logic includes address decoding for all onboard
resources, control and signal interpretation, DMA selection and
control logic, IRQ selection and control logic, and all interface
configuration logic.
The AD1821 supports a Type “F” DMA request/grant architec-
ture for transferring data with the ISA bus through the 8-bit
interface. The AD1821 also supports DACK preemption. Pro-
grammed I/O (PIO) mode is also supported for control register
accesses and for applications lacking DMA control. The
AD1821 includes dual DMA count registers for full-duplex
operation enabling simultaneous capture and playback on sepa-
rate DMA channels.
Codec Functional Description
The AD1821’s full-duplex stereo codec supports business audio
and multimedia applications. The codec includes stereo audio
converters, complete on-chip filtering, MPC Level-2 and
Level-3 compliant analog mixing, programmable gain and at-
tenuation, a variable sample rate converter, extensive digital mixing
and FIFOs buffering the Plug and Play ISA bus interface. When
using MODIO modem software, PHONE_IN and R_OUT
channels are used to support modem and telephony features.
Analog Inputs
The codec contains a stereo pair of
verters (ADC). Inputs to the ADC can be selected from the fol-
lowing analog signals: mono (PHONE_IN), mono microphone
(MIC), stereo line (LINE), external stereo synthesizer (SYNTH),
stereo CD ROM (CD), stereo audio from a video source (VID)
and post-mixed stereo or mono line output (OUT).
Analog Mixing
PHONE_IN, MIC, LINE, SYNTH, CD and VID can be mixed
in the analog domain with the stereo line OUT from the
digital-to-analog converters (DAC). Each channel of the stereo
analog inputs can be independently gained or attenuated from
+12 dB to –34.5 dB in 1.5 dB steps, except for PHONE_IN,
which has a range of 0 dB to –45 dB steps. The summing path
for the mono inputs (MIC, and PHONE_IN to line OUT) du-
plicates mono channel data on both the left and right line OUT,
which can also be gained or attenuated from +12 dB to –34.5 dB
in 1.5 dB steps for MIC, and +0 dB to –45.5 dB in 3 dB steps
for PHONE_IN. The left and right mono summing signals are
always identical being equally gained or attenuated.
Analog-to-Digital Datapath
The selector sends left and right channel information to the pro-
grammable gain amplifier (PGA). The PGA following the selec-
tor allows independent gain for each channel entering the ADC
from 0 dB to 22.5 dB in 1.5 dB steps.
For supporting time correlated I/O echo cancellation, the ADC
is capable of sampling microphone data on the left channel and
the mono summation of left and right OUT on the right channel.
The codec can operate in either a global stereo mode or a glo-
bal mono mode with left channel inputs appearing at both chan-
nels of the 16-bit
programmed sampling frequency (from 4 kHz to 55.2 kHz with
1 Hz resolution).
Digital Mixing & Sample Rates
The audio ADC sample rate and the audio DAC sample rates
converters. Data can be sampled at the
analog-to-digital con-
–14–
are completely independent. The AD1821 includes a variable
sample rate converter that lets the codec instantaneously
change and process sample rates from 4 kHz to 55.2 kHz with a
resolution of 1 Hz. The in-band integrated noise and distor-
tion artifacts introduced by rate conversions are below –90 dB.
Up to four channels of digital data can be summed together and
presented to the stereo DAC for conversion. Each digital chan-
nel pair can contain information encoded at a different sample
rate. For example, 8 kHz .wav data received from the ISA inter-
face, 48 kHz MPEG audio data received from I
44.1 kHz CD data received from I
22.05 kHz music data may be summed together and converted
by the DACs.
Digital-to-Analog Datapath
The internally generated music synthesizer data, PCM data
received from the ISA interface, data received from the I
port and data received from the I
port passes through an attenuation mute stage. The attenuator
allows independent control over each digital channel, which can
be attenuated from 0 dB to –94.5 dB in 1.5 dB steps before be-
ing summed together and passed to the DAC, or the channel
may be muted entirely.
Analog Outputs
The analog output of the DAC can be summed with any of the
analog input signals. The summed analog signal enters the
Master Volume stage where each channel L_OUT, R_OUT and
PHONE_OUT may be attenuated from 0 dB to –46.5 dB in
1.5 dB steps or muted.
Digital Data Types
The codec can process 16-bit twos-complement PCM linear
digital data, 8-bit unsigned magnitude PCM linear data and
8-bit -law or A-law companded digital data as specified in the
control registers. The AD1821 also supports ADPCM encoded
in the Creative SoundBlaster ADPCM formats.
Host-Based Echo Cancellation Support
The AD1821 supports time correlated I/O data format by pre-
senting MIC data on the left channel of the ADC and the mono
summation of left and right OUT on the right channel. The
ADC sample rates are independent of the DAC sample rate allow-
ing the AD1821 to support ADC time correlated I/O data at
8 kHz and DAC data at any other sample rate in the range of
4 kHz to 55.2 kHz simultaneously.
Telephony Support
The AD1821 contains a PHONE_IN input and a
PHONE_OUT output. These pins are supplied so the AD1821
may be connected to a modem chip set, a telephone handset or
down-line phone.
WSS and SoundBlaster Compatibility
Windows Sound System software audio compatibility is built
into the AD1821.
SoundBlaster emulation is provided through the SoundBlaster
register set and the internal music synthesizer. SoundBlaster Pro
version 2.01 functions are supported, including record and Cre-
ative SoundBlaster ADPCM.
Virtually all applications developed for SoundBlaster, Windows
Sound System, AdLib and MIDI MPU-401 platforms run on the
AD1821 SoundComm
process for the controller as you would for these other devices.
®
Controller. Follow the same development
2
S(1) port, and the DSP serial
2
S(1) and internally generated
2
S(0), digital
2
REV. 0
S(0)