AD1981BL Analog Devices, AD1981BL Datasheet - Page 26

• Manufacturer Part Number: AD1981BL
• Description: Low Voltage AC'97 Soundmax Codec
• Manufacturer: Analog Devices

AD1981BL
This register is not reset when the reset register (Register 00h) is written. All registers not shown and bits containing an X are assumed to be reserved.
SPLNK
SPDZ
SPAL
INTS
CHEN
REGM0
REGM1
REGM2
SLOT16
All registers not shown and bits containing an X are assumed to be reserved.
MBG[1:0]
VREFD
VREFH
Reg
No. Name D15
74h Serial
Reg
No. Name
76th Misc
Control Bits
Config-
uration
SLOT16 REGM2 REGM1 REGM0 X
SPDIF Link. This bit enables the SPDIF to link with the DAC for data requesting.
0 = SPDIF and DAC are not linked.
1 = SPDIF and DAC are linked and receive the same data requests (reset default).
SPDIF DACZ.
0 = Repeat last sample out of the SPDIF stream if FIFO underruns (reset default).
1 = Forces midscale sample out the SPDIF stream if FIFO underruns.
SPDIF ADC Loop-Around.
0 = SPDIF transmitter is connected to the ac-link stream (reset default).
1 = SPDIF transmitter is connected to the digital ADC stream, not the ac-link.
Interrupt Mode Select. This bit selects the JS interrupt implementation path.
0 = Bit 0 SLOT 12 (modem interrupt).
1 = Slot 6 valid bit (MIC ADC interrupt).
Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45).
0 = Disable chaining (reset default).
1 = Enable chaining into ID0 pin.
Master Codec Register Mask.
Slave 1 Codec Register Mask.
Slave 2 Codec Register Mask.
Enable 16-Bit Slot Mode. SLOT16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a
preferred mode for DSP serial port interfacing.
MIC Boost Gain Change Register.
These two bits allow changing the MIC preamp gain from the nominal 20 dB gain.
Note: This gain setting takes affect only while Bit D6 (M20) on the MIC volume register (0Eh) is set to 1; otherwise,
the MIC boost block has a gain of 0 dB.
00 = 20 dB gain (reset default).
01 = 10 dB gain.
10 = 30 dB gain.
11 = Reserved.
V
selection (see below).
0 = V
1 = V
V
0 = V
1 = V
D15
DACZ X
REFOUT
REFOUT
REFOUT
REFOUT
REFOUT
REFOUT
D14
D14 D13
Disable. Disables V
High. Changes V
MSPLT LODIS DAM X
pin is driven by the internal reference (reset default).
pin is placed into High Z Out mode.
pin is set to 2.25 V output (reset default).
pin is set to 2.25 V output.
D13
D12
Miscellaneous Control Bit Register (Index 76h)
REFOUT
D12
Serial Configuration Register (Index 74h)
REFOUT
D11
from 2.25 V to 3.70 V for MIC bias applications.
D10 D9
, placing it into High Z Out mode. Note that this bit overrides the VREFH bit
D11 D10 D9 D8
FMXE X
X
–26–
D8 D7
X
MADPD 2CMIC X
CHEN X
D7 D6 D5 D4
D6
X
D5 D4
X
MADST VREFH VREFD MBG1 MBG0 0000h
INTS X
D3
D3 D2
SPAL SPDZ SPLNK 7001h
D2
D1
D1
D0
D0
Default
REV. 0
Default