HY27SS16561A Hynix Semiconductor, HY27SS16561A Datasheet - Page 8

• Manufacturer Part Number: HY27SS16561A
• Description: (HY27xxxx561A) 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
• Manufacturer: Hynix Semiconductor

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1.2 PIN DESCRIPTION
Rev 0.5 / Jun. 2006
IO8-IO15(1)
NOTE:
1. For x16 version only
2. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple
the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required
during program and erase operations.
Pin Name
IO0-IO7
VCC
VSS
PRE
CLE
ALE
R/B
WE
WP
CE
RE
NC
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE).
ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Write Enable (WE).
CHIP ENABLE
This input controls the selection of the device. When the device is busy CE low does not deselect the
memory.
WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE.
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE which also increments the internal column address counter by
one.
WRITE PROTECT
The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)
operations.
READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
SUPPLY VOLTAGE
The VCC supplies the power for all the operations (Read, Write, Erase).
GROUND
NO CONNECTION
To Enable and disable the Lock mechanism and Power On Auto Read. When PRE is a logic high,
Block Lock mode and Power-On Auto-Read mode are enabled, and when PRE is a logic low, Block
Lock mode and Power-On Auto-Read mode are disabled. Power-On Auto-Read mode is available only
on 3.3V device.
Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it NC.
Table 2: Pin Description
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Description
HY27US(08/16)561A Series
HY27SS(08/16)561A Series
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