MPC8548E Freescale, MPC8548E Datasheet - Page 129
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MPC8548E
Manufacturer Part Number
MPC8548E
Description
Integrated Processor
Manufacturer
Freescale
Datasheet
1.MPC8548E.pdf
(142 pages)
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The AV
the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the
AV
the AV
and finally the 1 Ω resistor to the board supply plane. The capacitors are connected from AV
the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces
should be kept short, wide and direct.
Note the following:
21.3
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8548E system, and the device
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each V
of the device. These decoupling capacitors should receive their power from separate V
OV
minimize inductance. Capacitors must be placed directly under the device using a standard escape pattern
as much as possible. If some caps are to be placed surrounding the part it should be routed with large trace
to minimize the inductance.
These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capacitors
should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating
to ensure the quick response time necessary. They should also be connected to the power and ground
planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor
for best values, types and quantity of bulk capacitors.
Freescale Semiconductor
DD
DD
•
•
_SRDS ball to ensure it filters out as much noise as possible. The ground connection should be near
, GV
DD
AV
Signals on the SerDes interface are fed from the XV
DD
_SRDS ball. The 0.003-µF capacitor is closest to the ball, followed by the two 2.2 µF capacitors,
Decoupling Recommendations
_SRDS signal provides power for the analog portions of the SerDes PLL. To ensure stability of
DD
DD
_SRDS should be a filtered version of SV
DD
, LV
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
, TV
SV
DD
Note:
1. An 0805 sized capacitor is recommended for system initial bring-up.
DD
DD
, and GND power planes in the PCB, utilizing short low impedance traces to
, BV
DD
1.0 Ω
Figure 59. SerDes PLL Power Supply Filter
, OV
DD
, GV
2.2 µF
DD
1
, and LV
GND
2.2 µF
DD
DD
DD
.
, planes, to enable quick recharging of the
1
, TV
DD
power plane.
DD
0.003 µF
, BV
DD
, OV
AV
DD
DD
_SRDS
, GV
System Design Information
DD
DD
, TV
, and LV
DD
DD
_SRDS to
, BV
DD
DD
pin
129
,