MPC8548E Freescale, MPC8548E Datasheet - Page 84

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

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Serial RapidIO
17.8
For each baud rate at which an LP-serial receiver is specified to operate, the receiver shall meet the
corresponding bit error rate specification
receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the receiver
input compliance mask shown in
the receiver test signal is measured at the input pins of the receiving device with the device replaced with
a 100-Ω ± 5% differential resistive load.
17.9
Since the LP-serial electrical specification are guided by the XAUI electrical interface specified in
Clause 47 of IEEE Std. 802.3ae-2002, the measurement and test requirements defined here are similarly
guided by Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002
84
Receiver Eye Diagrams
Measurement and Test Requirements
–V
–V
Table 64. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
V
V
DIFF
DIFF
DIFF
DIFF
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
max
max
min
min
0
1.25 GBaud
2.5 GBaud
3.125 GBaud
0
Receiver Type
Figure 54. Receiver Input Compliance Mask
Figure 54
V
(Table
DIFF
A
(mV)
100
100
100
with the parameters specified in
min
61,
B
Table
V
DIFF
(mV)
800
800
800
Time (UI)
max
62,
Table
A (UI)
0.275
0.275
0.275
1-B
63) when the eye pattern of the
1-A
Table
B (UI)
0.400
0.400
0.400
64. The eye pattern of
Freescale Semiconductor
1