MPC8548E Freescale, MPC8548E Datasheet - Page 131

• Manufacturer Part Number: MPC8548E
• Description: Integrated Processor
• Manufacturer: Freescale

www.DataSheet4U.com
21.7
The MPC8548E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I
To measure Z
or GND. Then, the value of each resistor is varied until the pad voltage is OV
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R
OV
other in value. Then, Z
Table 81
nominal OV
21.8
The MPC8548E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip gated resistor of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to pull
Freescale Semiconductor
Note: Nominal supply voltages. See
DD
Impedance
/2. R
R
R
summarizes the signal impedance targets. The driver impedances are targeted at minimum V
Output Buffer DC Impedance
N
P
Configuration Pin Muxing
P
DD
then becomes the resistance of the pull-up devices. R
0
for the single-ended drivers, an external resistor is connected from the chip pad to OV
, 105°C.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 4
Local Bus, Ethernet, DUART, Control,
Configuration, Power Management
0
= (R
P
+ R
43 Target
43 Target
Figure 60. Driver Impedance Measurement
Table
Data
N
Table 81. Impedance Characteristics
)/2.
1, T
j
= 105°C.
2
25 Target
25 Target
C).
PCI
P
Pad
R
R
is trimmed until the voltage at the pad equals
OGND
OV
N
P
DD
P
and R
SW2
SW1
DDR DRAM
20 Target
20 Target
N
are designed to be close to each
DD
/2 (see
System Design Information
Symbol
Z
Z
Figure
0
0
60). The
Unit
W
W
DD
DD
131
,