MD3331-D32-V3Q18 M-Systems Inc., MD3331-D32-V3Q18 Datasheet - Page 18

• Manufacturer Part Number: MD3331-D32-V3Q18
• Description: Mobile Diskonchip Plus 128Mbits 1.8V I/o
• Manufacturer: M-Systems Inc.

3.2
The system interface block provides an easy-to-integrate SRAM-like (also EEPROM-like) interface to Mobile
DiskOnChip Plus, enabling it to interface with various CPU interfaces, such as a local bus, ISA bus, SRAM
interface, EEPROM interface or any other compatible interface. In addition, the EEPROM-like interface enables
direct access to the Programmable Boot Block to permit XIP functionality during system initialization.
A 13-bit wide address bus enables access to the DiskOnChip 8KB memory window (as shown in Section 6.2). The
16-bit data bus permits 16-bit wide access to the host. The internal access to the flash is 8-bit.
The Chip Enable (CE#), Write Enable (WE#) and Output Enable (OE#) signals trigger read and write cycles. A
write cycle occurs while both the CE# and the WE# inputs are asserted. Similarly, a read cycle occurs while both the
CE# and OE# inputs are asserted. Note that Mobile DiskOnChip Plus does not require a clock signal. Mobile
DiskOnChip Plus features a unique analog static design, optimized for minimal power consumption. The CE#, WE#
and OE# signals trigger the controller (e.g., system interface block, bus control and data pipeline) and flash access.
The Reset In (RSTIN#) and Busy (BUSY#) control signals are used in the reset phase. See Section 5.2 for further
details.
The Interrupt Request (IRQ#) signal can be used when long I/O operations, such as Block Erase, delay the CPU
resources. The signal is also asserted when a Data Protection violation has occurred. When this signal is
implemented, the CPU can run other tasks and only returns to continue read/write operations with Mobile
DiskOnChip Plus after the IRQ# signal has been asserted and an Interrupt Handling Routine (implemented in the
OS) has been called to return control to the TrueFFS driver.
3.3
The Configuration Interface block enables the designer to configure Mobile DiskOnChip Plus to operate in different
modes. The identification signals (ID[1:0]) are used for identifying the relevant DiskOnChip device in a cascaded
configuration (see Section 9.6 on cascading for further details). The Lock (LOCK#) signal enables hard-wire
hardware-controlled protection of code and data, as described below. For a standard interface, the Interface
Configuration (IF_CFG) signal configures Mobile DiskOnChip Plus for 16-bit or 8-bit data access (see Section 9.5.4).
3.4
The protection and security-enabling block, consisting of read/write protection, UID and OTP area, enables
advanced data and code security and protection. Located on the main route of traffic between the host and the flash,
this block monitors and controls all data and code transactions to and from Mobile DiskOnChip Plus.
3.4.1 Read/Write Protection
Data and code protection is implemented through a Protection State Machine (PSM). The user can configure one or two
independently programmable areas of the flash memory as read protected, write protected, or read/write protected.
A protection area may be protected by either/both of these hardware mechanisms:
The size and location of each area is user-defined to provide maximum flexibility for the target platform and
application requirements.
The configuration parameters of the protected areas are stored on the flash media and are automatically downloaded
from the flash to the PSM upon power-up, to enable robust protection throughout the flash lifetime.
In the event of an attempt to bypass the protection mechanism, illegally modify the protection key or in any way
sabotage the configuration parameters, the entire DiskOnChip becomes both read and write protected, and is
completely inaccessible.
For further information on the hardware protection mechanism, refer to Section 4.
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System Interface
Configuration Interface
Protection and Security-Enabling Features
64-bit protection key
Hard-wired LOCK# signal
Data Sheet, Rev. 1.7
Mobile DiskOnChip Plus 16/32MByte 1.8V I/O
95-SR-000-10-8L