AD1876JN Analog Devices, AD1876JN Datasheet - Page 5

• Manufacturer Part Number: AD1876JN
• Description: 16-Bit 100 kSPS Sampling ADC
• Manufacturer: Analog Devices

REV. A
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type: AI = Analog Input.
DI = Digital Input.
DO = Digital Output.
P = Power.
Name
SAMPLE
CLK
D
DGND
V
N/C
N/C
AGND
AGND SENSE
V
V
V
V
D
BUSY
CAL
CC
IN
EE
DD
REF
OUT
OUT
CLK
SAMPLE
DGND
AGND
D
CLK
OUT
V
NC
NC
CC
Package Pinout
1
2
3
4
5
6
7
8
NC = NO CONNECT
(Not to Scale)
TOP VIEW
AD1876
Type
DI
DI
DO
P
P
–
–
P/AI
AI
AI
AI
P
P
DO
DO
DI
16
15
14
13
12
11
10
9
Description
V
Sample-Hold Amplifier and initiates conversion (see “Conversion Control” paragraph). Dur-
ing calibration, SAMPLE is active HIGH, forcing D
during calibration, D
Master Clock Input. The AD1876 requires 17 clock pulses to execute a conversion. CLK is
also used to derive D
Serial Output Data, Twos Complement format.
Digital Ground.
+12 V Analog Supply Voltage.
No Connection.
No Connection.
Analog Ground.
Analog Ground Sense.
Analog Input Voltage, referred the AGND SENSE.
External Voltage Reference Input, referred to AGND.
–12 V Analog Supply Voltage.
+5 V Logic Supply Voltage.
The rising edge of D
CLK.
Status Line for Converter. Active HIGH, indicating a conversion or calibration in progress.
Calibration Control Pin (asynchronous).
CAL
BUSY
D
V
V
V
V
AGND SENSE
OUT
DD
EE
REF
IN
IN
CLK
Acquisition Control Pin. During conversion, SAMPLE controls the state of the internal
PIN DESCRIPTION
OUT
OUT
OUT
will output diagnostic information (See “Autocalibration” paragraph.)
CLK may be used to latch D
CLK (Pin 14). During calibration, 5000 clock pulses are applied.
–5–
AGND SENSE
SAMPLE
AGND
V
CAL
CLK
REF
V
IN
10
16
11
9
8
2
1
Functional Block Diagram
BUFFERS
MICROCODED
CONTROLLER
INPUT
OUT
OUT
LEVEL TRANSLATORS
(Pin 3) LOW. If SAMPLE is LOW
LOGIC TIMING
(Pin 3). D
CAL
DAC
16-BIT
DAC
RAM
SAR
ALU
OUT
COMP
D CHIP
AD1876
CLK is derived from
A CHIP
AD1876
15 BUSY
14
3
D
D
OUT
OUT
CLK