MT28C3224P20 Micron Technology, MT28C3224P20 Datasheet - Page 24

• Manufacturer Part Number: MT28C3224P20
• Description: FLASH AND SRAM COMBO MEMORY
• Manufacturer: Micron Technology

STANDBY MODE
HIGH level on F_CE# and F_RP# to enter the standby
mode. In the standby mode, the outputs are placed in
High-Z. Applying a CMOS logic HIGH level on F_CE#
and F_RP# reduces the current to I
device is deselected during an ERASE operation or dur-
ing programming, the device continues to draw cur-
rent until the operation is complete.
AUTOMATIC POWER SAVE (APS) MODE
ods when the Flash array is not being read and the
device is in the active mode. During this time the de-
vice switches to the automatic power save (APS) mode.
When the device switches to this mode, I
to a level comparable to I
be realized by applying a logic HIGH level on CE# to
place the device in standby mode. The low level of
power is maintained until another operation is initi-
ated. In this mode, the I/Os retain the data from the
last memory address read until a new address is read.
This mode is entered automatically if no addresses or
control signals toggle.
V
VOLTAGES
programming and erase with V
In addition to the flexible block locking, the V
gramming voltage can be held LOW for absolute hard-
ware write protection of all blocks in the Flash device.
When V
eration results in an error, prompting the correspond-
ing status register bit (SR3) to be set.
and erase with V
of 100 cycles and 10 cumulative hours. The device
can withstand 100,000 WRITE/ERASE operations when
V
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
PP
PP
Icc supply current is reduced by applying a logic
Substantial power savings are realized during peri-
The Flash memory devices provide in-system
A factory option provides in-system programming
V
= V
/V
PP
CC
CC
at 12V ±5% (V
PP
.
PROGRAM AND ERASE
is below V
PP
in the 0.0V–2.2V range.
PPLK
PP
2
) is supported for a maximum
, any PROGRAM or ERASE op-
CC
3
. Further power savings can
PP
in the 0.9V–2.2V range.
CC
3
(MAX). If the
CC
is reduced
PP
pro-
24
256K x 16 SRAM COMBO MEMORY
monitors the V
tions are allowed only when V
specified in Table 10.
WRITE/ERASE operation is prevented.
DEVICE RESET
be asserted (RST# = V
reset, the device can be accessed for a READ operation
with a delayed access time of
of RST#. The circuitry used for generating the RST#
signal needs to be common with the rest of the system
reset to ensure that correct system initialization occurs.
Please refer to the timing diagram for further details.
POWER-UP SEQUENCE
to properly initialize internal chip operations:
should be brought to V
the rise time of RST# (10%–90%) should be < 10µs.
During WRITE and ERASE operations, the WSM
When V
To correctly reset the device, the RST# signal must
The following power-up sequence is recommended
• At power-up, RST# should be kept at V
• V
• V
When the power-up sequence is completed, RST#
In-Factory
In-System
DEVICE
after V
integrity.
CC
PP
Q should not come up before V
should be kept at V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CC
CC
2 MEG x 16 PAGE FLASH
is below V
reaches V
PP
V
voltage level. WRITE/ERASE opera-
PP
Table 10
Ranges (V)
IL
IH
) for a minimum of
LKO
CC
. To ensure proper power-up,
(MIN).
MIN
11.4
or V
t
IL
0.9
RWH from the rising edge
to maximize data
PP
PP
is within the ranges
is below V
©2002, Micron Technology, Inc.
CC
ADVANCE
.
MAX
IL
12.6
t
2.2
RP. After
PPLK
for 2µs
, any