MT58L256L36D Micron Semiconductor, MT58L256L36D Datasheet - Page 22

• Manufacturer Part Number: MT58L256L36D
• Description: (MT58Lxxxx) 8Mb SYNCBURST SRAM
• Manufacturer: Micron Semiconductor

WRITE TIMING PARAMETERS
NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
MT58L512L18D_D.p65 – Rev. 2/02
SYMBOL
t
f
t
t
t
t
t
t
t
KC
KF
KH
KL
OEHZ
AS
ADSS
AAS
WS
BWa#-BWd#
ADDRESS
(NOTE 2)
ADSC#
ADSP#
BWE#,
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or by GW# HIGH, BWE# LOW and BWa#-BWb# LOW for x18 device;
ADV#
GW#
OE#
CLK
CE#
MIN
6.0
2.3
2.3
1.5
1.5
1.5
1.5
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
output data contention for the time period prior to the byte write enable inputs being sampled.
or GW# HIGH, BWE# LOW and BWa#-BWd# LOW for x32 and x36 devices.
D
Q
-6
BURST READ
MAX
166
3.5
High-Z
t ADSS
t CES
t AS
MIN
7.5
2.5
2.5
1.5
1.5
1.5
1.5
A1
t ADSH
t CEH
t AH
t KH
t OEHZ
(NOTE 3)
-7.5
Byte write signals are ignored for first cycle when
ADSP# initiates burst.
t KC
t ADSS
MAX
t KL
133
4.2
Single WRITE
t DS
D(A1)
t ADSH
t DH
MIN
3.0
3.0
2.0
2.0
2.0
2.0
10
A2
-10
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
(NOTE 4)
MAX
100
4.5
D(A2)
WRITE TIMING
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
D(A2 + 1)
(NOTE 1)
(NOTE 5)
t WS
BURST WRITE
22
t WH
SYMBOL
t
t
t
t
t
t
t
t
D(A2 + 1)
DS
CES
AH
ADSH
AAH
WH
DH
CEH
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ADV# suspends burst.
MIN
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
D(A2 + 2)
-6
ADSC# extends burst.
MAX
D(A2 + 3)
MIN
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
t ADSS
-7.5
A3
D(A3)
t ADSH
MAX
DON’T CARE
Extended BURST WRITE
t AAS
t WS
D(A3 + 1)
MIN
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
t AAH
t WH
©2002, Micron Technology, Inc.
-10
UNDEFINED
MAX
D(A3 + 2)
UNITS
ns
ns
ns
ns
ns
ns
ns
ns