MT58L256L36D Micron Semiconductor, MT58L256L36D Datasheet - Page 8

• Manufacturer Part Number: MT58L256L36D
• Description: (MT58Lxxxx) 8Mb SYNCBURST SRAM
• Manufacturer: Micron Semiconductor

TQFP PIN DESCRIPTIONS (CONTINUED)
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
MT58L512L18D_D.p65 – Rev. 2/02
62, 63, 68, 69, 56-59, 62, 63
13, 18, 19, 22, 72-75, 78, 79
14, 15, 41, 65, 14, 15, 41, 65,
26, 40, 55, 60, 26, 40, 55, 60,
66, 75, 78, 79,
43 (T Version) 43 (T Version)
16, 25, 28-30,
51-53, 56, 57,
54, 61, 70, 77 54, 61, 70, 77
67, 71, 76, 90 67, 71, 76, 90
4, 11, 20, 27,
5, 10, 17, 21,
(b) 8, 9, 12,
(a) 58, 59,
1-3, 6, 7,
72, 73
38, 39
95, 96
x18
84
85
31
23
74
24
91
42
–
–
22-25, 28, 29
4, 11, 20, 27,
5, 10, 17, 21,
(c) 2, 3, 6-9,
(a) 52, 53,
(d) 18, 19,
(b) 68, 69
x32/x36
12, 13
38, 39
16, 66
84
85
31
51
80
30
91
42
1
SYMBOL
NF/DQPb
NF/DQPd
NF/DQPa
NF/DQPc
ADSC#
ADSP#
MODE
V
DQb
DQd
DNU
DQa
DQc
V
V
NC
NF
DD
DD
SS
Q
Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins;
Supply Power Supply: See DC Electrical Characteristics and Operating
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Supply Ground: GND.
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b”
TYPE
Input Synchronous Address Status Controller: This active LOW input
Input Synchronous Address Status Processor: This active LOW input
Input Mode: This input selects the burst sequence. A LOW on this pin
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
NF/
I/O
–
–
–
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
selects “linear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins.
Input data must meet setup and hold times around the rising edge
of CLK.
No Function/Parity Data I/Os: On the x32 version, these pins are No
Function (NF). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
Conditions for range.
Operating Conditions for range.
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
No Connect: These signals are not internally connected and may be
connected to ground to improve package heat dissipation.
No Function: These pins are internally connected to the die and
have the capacitance of an input pin. It is allowable to leave these
pins unconnected or driven by signals. On the S Version, pin 42 is
reserved as an address upgrade pin for the 16Mb SyncBurst SRAM.
8
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2002, Micron Technology, Inc.