MT9045 Zarlink Semiconductor, MT9045 Datasheet - Page 13

• Manufacturer Part Number: MT9045
• Description: T1/E1/OC3 System Synchronizer
• Manufacturer: Zarlink Semiconductor

MT9045
Data Sheet
Capture Range
Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull
±
into synchronization. The MT9045 capture range is equal to
230 ppm minus the accuracy of the master clock
(OSCi). For example, a 32 ppm master clock results in a capture range of 198 ppm.
The Bellcore GR-1244-CORE standard, recommends that the PLL should be able to reject references that are off
±
the nominal frequency by more than
17 ppm. The MT9045 provides two pins, PRIOOR and SECOOR, to indicate
±
whether the primary and secondary reference are within the
17 ppm of the nominal frequency. Both references
are monitored at the same time. PRIOOR and SECOOR are updated every 1.0 to 1.5 second.
The PRIOOR and SECOOR pins on the MT9045 indicate whether the Primary and Secondary references are
within +/- 17ppm of the PLL center frequency. If the Master Oscillator clock input at the OSCi pin has an accuracy of
+/-4.6ppm then the effective out of range limits of the PRIOOR and SECOOR pins will be +/-21.6ppm.
If there are no clock transitions at the Primary and Secondary reference inputs when the MT9045 is configured to
operate with 8kHz or 19.44MHz, then the PRIOOR and SECOOR pins will provide a 50ns high pulse width
occurring once every 1.26 seconds. The duration of the pulse width is dependent on the master clock frequency. If
there are no clock transitions at the active reference pin, the MT9045 will automatically go to Holdover Mode and
indicate this condition with the Holdover pin.
Lock Range
This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock
range is equal to the capture range for the MT9045.
Phase Slope
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect
to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is
nominally equal to the value of the final output signal or final input signal.
Time Interval Error (TIE)
TIE is the time delay between a given timing signal and an ideal timing signal.
Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
MTIE S ( )
TIEmax t ( ) TIEmin t ( )
=
–
Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a
mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has
settled to a steady state.
±
In the case of the MT9045, the output signal phase continuity is maintained to within
5ns at the instance (over one
frame) of all reference switches and all mode changes. The total phase shift, depending on the switch or type of
mode change, may accumulate up to 200 ns over many frames. The rate of change of the 200 ns phase shift is
limited to a maximum phase slope of approximately 5ns/125us. This meets the AT&T TR62411 maximum phase
slope requirement of 7.6ns/125us and Bellcore GR-1244-CORE (81ns/1.326ms).
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Zarlink Semiconductor Inc.