MT9045 Zarlink Semiconductor, MT9045 Datasheet - Page 2

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MT9045

Manufacturer Part Number
MT9045
Description
T1/E1/OC3 System Synchronizer
Manufacturer
Zarlink Semiconductor
Datasheet

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Description
The MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing
and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links.
The MT9045 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048MHz,
1.544MHz, or 8kHz input reference.
The MT9045 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced, and
Stratum 4 and ETSI ETS 300 011; and ITU-T G.813 Option 1 for 2048 kbit/s interfaces. It will meet the jitter/wander
tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope,
holdover frequency and MTIE requirements for these specifications.
SECOOR
FLOCK
LOCK
C1.5o
OSCo
TCLR
C19o
OSCi
F16o
RSP
SEC
RST
TSP
Vdd
C2o
V
C4o
Vdd
PRI
Vss
F0o
F8o
Vss
SS
IC
Figure 2 - Pin Connections
Zarlink Semiconductor Inc.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
MT9045
SSOP
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TMS
TCK
TRST
TDI
TDO
PRIOOR
IC
FS1
FS2
IC
RSEL
MS1
MS2
Vdd
IC
IC
NC
Vss
PCCi
HOLDOVER
Vdd
C6o
C16o
C8o
Data Sheet

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