MT9045 Zarlink Semiconductor, MT9045 Datasheet - Page 7

• Manufacturer Part Number: MT9045
• Description: T1/E1/OC3 System Synchronizer
• Manufacturer: Zarlink Semiconductor

MT9045
Data Sheet
Digital Phase Lock Loop (DPLL)
As shown in Figure 4, the DPLL of the MT9045 consists of a Phase Detector, Limiter, Loop Filter, Digitally
Controlled Oscillator, and a Control Circuit.
Virtual Reference
DPLL Reference
Phase
Digitally
from
to
Detector
Limiter
Loop Filter
Controlled
TIE Corrector
Output Interface Circuit
Oscillator
State Select
Control
Feedback Signal
from
Circuit
from
Input Impairment Monitor
Frequency Select MUX
State Select
from
State Machine
Figure 4 - DPLL Block Diagram
Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the
feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase
difference between the two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the
proper feedback signal to be externally selected (e.g., 8kHz, 1.544MHz, 2.048MHz or 19.44MHz).
Limiter - the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all
input transient conditions with a maximum output phase slope of 5ns per 125us. This is well within the maximum
phase slope of 7.6ns per 125us or 81ns per 1.326ms specified by AT&T TR62411 and Bellcore GR-1244-CORE,
respectively.
Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four
reference frequency selections (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). This filter ensures that the jitter transfer
requirements in ETS 300 011 and AT&T TR62411 are met.
Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input
Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the MT9045.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover Mode, the DCO is free running at a frequency equal to the last (less 30ms to 60ms) frequency the DCO
was generating while in Normal Mode.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source.
Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical
to the line frequency), and the input phase offset is small enough such that no phase slope limiting is exhibited, then
the lock signal will be set high. For specific Lock Indicator design recommendations see the Applications - Lock
Indicator section.
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Zarlink Semiconductor Inc.