MT9045 Zarlink Semiconductor, MT9045 Datasheet - Page 3

• Manufacturer Part Number: MT9045
• Description: T1/E1/OC3 System Synchronizer
• Manufacturer: Zarlink Semiconductor

Pin Description
23,31
28,35
Pin #
1,10,
7,17
12
13
14
15
11
2
3
4
5
6
8
9
SECOOR Secondary Reference Out Of Capture Range (Output). A logic high at this pin indicates
Name
OSCo
TCLR
OSCi
F16o
SEC
RSP
RST
TSP
PRI
V
F0o
F8o
V
DD
SS
Ground. 0 Volts. (Vss pads).
Reset (Input). A logic low at this input resets the MT9045. To ensure proper operation, the
device must be reset after reference signal frequency changes and power-up. The RST pin
should be held low to a minimum of 300ns. While the RST pin is low, all frame pulses except
RST and TSP and all clock outputs except C6o, C16o and C19o are at logic high. The RST,
TSP, C6o, C16o are at logic low during reset. The C19o is free-running during reset. Following
a reset, the input reference source and output clocks and frame pulses are phase aligned as
shown in Figure 13.
TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a realignment of input phase with output phase as shown in
Figure 13. The TCLR pin should be held low for a minimum of 300ns. This pin is internally
pulled down to VSS.
that the secondary reference is off the nominal frequency by more than
Secondary Reference (Input).
(falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz,
2.048MHz or 19.44MHz) may be used. The selection of the input reference is based upon the
MS1, MS2, RSEL, and PCCi control inputs.This pin is internally pulled up to V
Primary Reference (Input). See pin description for SEC. This pin is internally pulled up to
V
Positive Supply Voltage. +3.3V
Oscillator Master Clock (CMOS Output).
connected from this pin to OSCi, see Figure 9. Not suitable for driving other devices. For clock
oscillator operation, this pin is left unconnected, see Figure 8.
Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is
connected from this pin to OSCo, see Figure 9. For clock oscillator operation, this pin is
connected to a clock source, see Figure 8.
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 8.192 Mb/s. See Figure 14.
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 2.048Mb/s and 4.096Mb/s. See Figure 14.
Receive Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 15.
Transmit Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 15.
Frame Pulse (CMOS Output). This is an 8kHz 122ns active high framing pulse, which marks
the beginning of a frame. See Figure 14.
DD
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Zarlink Semiconductor Inc.
MT9045
DC
This is one of two (PRI & SEC) input reference sources
3
nominal.
Description
For crystal operation, a 20MHz crystal is
±
17 ppm.
DD
Data Sheet
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