AD630 Analog Devices, AD630 Datasheet - Page 5

• Manufacturer Part Number: AD630
• Description: Balanced Modulator/Demodulator
• Manufacturer: Analog Devices

CIRCUIT DESCRIPTION
The simplified schematic of the AD630 is shown in Figure 14.
It has been subdivided into three major sections, the comparator,
the two input stages and the output integrator. The comparator
consists of a front end made up of Q52 and Q53, a flip-flop load
formed by Q3 and Q4, and two current steering switching cells
Q28, Q29 and Q30, Q31. This structure is designed so that a
differential input voltage greater than 1.5 mV in magnitude
applied to the comparator inputs will completely select one the
switching cells. The sign of this input voltage determine which
of the two switching cells is selected.
The collectors of each switching cell connect to an input trans-
conductance stage. The selected cell conveys bias currents i
and i
The deselected cell blocks the bias to its input stage which, as a
consequence, remains off.
The structure of the transconductance stages is such that they
present a high impedance at their input terminals and draw no
bias current when deselected. The deselected input does not
interfere with the operation of the selected input insuring maxi-
mum channel separation.
Another feature of the input structure is that it enhances the
slew rate of the circuit. The current output of the active stage
follows a quasi-hyperbolic-sine relationship to the differential
input voltage. This means that the greater the input voltage, the
harder this stage will drive the output integrator, and hence, the
+V
–V
SEL B
SEL A
S
S
10
11
9
8
23
Q3
to the input stage it controls, causing it to become active.
Q52
V
i
V
i
Q53
CH A–
i55
Q4
20
10k
5k
5k
R
OFF ADJ
R
R
A
10k
A
B
DIFF
Q62
Q28
R
i22
3
Q33
B
Q29
Q30
R
OFF ADJ
Q34
F
CH A+
DIFF
i23
10k
Q65
10k
4
R
F
2
Q31
CH B+
19
Q24
Q67
OFF ADJ
Q35
CM
V
5
O
V
=
O
Q36
(
= –
Q70
1+
Q25
OFF ADJ
C122
R
R
R
R
C121
CM
i73
F
B
F
A
CH B–
6
18
)
V
V
i
Q32
i
Q44
Q74
COMP
13
12
22
V
O
faster the output signal will move. This feature helps insure
rapid, symmetric settling when switching between inverting and
noninverting closed loop configurations.
The output section of the AD630 includes a current mirror-load
(Q24 and Q25), an integrator-voltage gain stage (Q32), and
complementary output buffer (Q44 and Q74). The outputs of
both transconductance stages are connected in parallel to the
current mirror. Since the deselected input stage produces no
output current and presents a high impedance at its outputs,
there is no conflict. The current mirror translates the differential
output current from the active input transconductance amplifier
into single ended form for the output integrator. The comple-
mentary output driver then buffers the integrator output pro-
duce a low impedance output.
OTHER GAIN CONFIGURATIONS
Many applications require switched gains other than the ± 1 and
± 2 which the self-contained applications resistors provide. The
AD630 can be readily programmed with three external resistors
over a wide range of positive and negative gain by selecting and
R
R
magnitude equals the noninverting magnitude, the value of R
found to be R
combination of R
The feedback synthesis of the AD630 may also include reactive
impedance. The gain magnitudes will match at all frequencies if
the A impedance is made to equal the parallel combination of
the B and F impedances. Essentially the same considerations
apply to the AD630 as to conventional op-amp feedback circuits.
Virtually any function which can be realized with simple nonin-
verting “L network” feedback can be used with the AD630. A
common arrangement is shown in Figure 15. The low frequency
gain of this circuit is 10. The response will have a pole (–3 dB)
at a frequency f
high frequency asymptote) at about 10 times this frequency.
The 2k resistor in series with each capacitor mitigates the load-
ing effect on circuitry driving this circuit, eliminates stability
problems, and has a minor effect on the pole-zero locations.
As a result of the reactive feedback, the high frequency components
of the switched input signal will be transmitted at unity gain
while the low frequency components will be amplified. This
arrangement is useful in demodulators and lock-in amplifiers. It
increases the circuit dynamic range when the modulation or
interference is substantially larger than the desired signal ampli-
tude. The output signal will contain the desired signal multi-
plied by the low frequency gain (which may be several hundred
for large feedback ratios) with the switching signal and interfer-
ence superimposed at unity gain.
B
A
and R
to give the desired inverting gain. Note that when the inverting
F
to give the noninverting gain 1 + R
V
i
B
R
F
B
/(R
C
and R
1/(2 π 100 kΩC) and a zero (3 dB from the
11.11k
10k
B
2k
+ R
10
9
F
to match positive and negative gain.
F
). That is, R
20
19
18
2
2k
100k
A
B
A
should equal the parallel
12
C
13
F
/R
7
8
–V
B
and subsequent
S
AD630
V
O
A
is