D7225G NEC, D7225G Datasheet - Page 22

• Manufacturer Part Number: D7225G
• Description: Search -----> UPD7225G
• Manufacturer: NEC

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6.
conditions:
22
When a low level of 12 clock cycles or more is input to the /RESET pin, the PD7225 will be reset to the following
• This condition is the same as when M2
• Display data transfer from the data memory to the display data latch
• Command/data register output
• LCD display
Function when the PD7225 is reset
• S0-S31 and COM0-COM3 pins output V
• Serial data input
When used in a multi-chip system, the reset state must be released (rising edge of /RESET) within 5 s.
RESET FUNCTION
the UNSYNCHRONIZED TRANSFER command is executed.
command is executed.
executed.
This condition is the same as when the DISPLAY OFF or the BRINKING OFF command is
Disabled (/BUSY = 0) (However, /CS = 0)
/RESET
Figure 6-1. Reset Signal in Multi-Chip System
This condition is the same as when the WITHOUT SEGMENT DECODER
DD
Data Sheet S14308EJ6V0DS00
M0 = 0, F1, F0 = 0 are executed by the MODE SET command.
12 clock cycles
5 s max.
0.3V
0.7V
DD
DD
This condition is the same as when
PD7225