TDA8029 Philips Semiconductors, TDA8029 Datasheet - Page 22

• Manufacturer Part Number: TDA8029
• Description: Low power single card reader
• Manufacturer: Philips Semiconductors

Philips Semiconductors
8.4
The TDA8029 has a 6-source 4-level interrupt structure.
There are three SFRs associated with the 4-level interrupt: IE, IP and IPH. The Interrupt Priority High (IPH) register
implements the 4-level interrupt structure. The IPH is located at SFR address B7h.
The function of the IPH is simple and when combined with the IP determines the priority of each interrupt. The priority of
each interrupt is determined as shown in Table 20.
Table 20 Priority bits
Table 21 Interrupt table
Notes
1. Level activated.
2. Transition activated.
8.4.1
Table 22 Interrupt enable register bits
Table 23 Description of register bits
2003 Oct 30
X0
T0
X1
T1
SP
T2
Symbol
Low power single card reader
BIT
BIT
7
6
5
4
3
IPH BIT n
Interrupt priority structure
SOURCE
I
NTERRUPT
0
0
1
1
EA
ET2
ES
ET1
SYMBOL
EA
E
7
NABLE
POLLING PRIORITY
(IE)
Global disable. If EA = 0, all interrupts are disabled; If EA = 1, each interrupt can be
individually enabled or disabled by setting or clearing its enable bit.
Not implemented. Reserved for future use; note 2.
Timer 2 interrupt enable. ET2 = 1 enables the interrupt; ET2 = 0 disables the interrupt.
Serial port interrupt enable. ES = 1 enables the interrupt; ES = 0 disables the interrupt.
Timer 1 interrupt enable. ET1 = 1 enables the interrupt; ET1 = 0 disables the interrupt.
IP BIT n
REGISTER
6
0
1
0
1
1
2
3
4
5
6
ET2
5
level 0 (lowest priority)
level 1
level 2
level 3 (highest priority)
REQUEST BITS
TF2, EXF2
RI, TI
TF0
TF1
IE0
IE1
22
ES
4
DESCRIPTION
INTERRUPT PRIORITY LEVEL
ET1
HARDWARE CLEAR
3
N
N
(1)
(1)
(1)
Y
Y
N
N
; Y
; Y
EX1
(2)
(2)
2
VECTOR ADDRESS
ET0
Product specification
1
TDA8029
(HEX)
0B
1B
2B
03
13
23
EX0
0