TDA8029 Philips Semiconductors, TDA8029 Datasheet - Page 40

• Manufacturer Part Number: TDA8029
• Description: Low power single card reader
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 64 Description of register bits
Table 65 Clock value for an asynchronous card
2003 Oct 30
Low power single card reader
7 and 6
2 to 0
BIT
5
4
3
AC2
0
0
0
0
1
1
1
1
SHL
CST
SC
AC[2:0]
SYMBOL
Not used.
Select HIGH Level. This bit determines how the clock is stopped when bit CST = 1. If
SHL = 0, then the clock is stopped at LOW level, if SHL = 1 at HIGH level.
Clock Stop. In case of an asynchronous card, bit CST defines whether the clock to the
card is stopped or not. If CST = 1, then the clock is stopped. If CST = 0, then the clock is
determined by bits AC[2:0] according to Table 65. All frequency changes are
synchronous, ensuring that no spike or unwanted pulse width occurs during changes
Synchronous Clock. In the event of a synchronous card, then pin CLK is the copy of the
value of bit SC. In reception mode, the data from the card is available to bit UR0 after a
read operation of register URR. In transmission mode, the data is written on the I/O line
of the card when register UTR has been written to.
Asynchronous card clock. When CST = 0, the clock is determined by the state of these
bits according to Table 65.
f
For switching from
and AC0 must remain the same). For switching from
and reverse, only bits CST and SHL must be changed.
When switching from
command and the effective frequency change on pin CLK. The fastest switch is from
1
reverse. The bit CLKSW in register MSR tells the effective switch moment.
In case of f
pin XTAL1.
int
/
2
f
is the frequency delivered by the internal oscillator clock circuitry.
XTAL
to
1
CLK
/
2
AC1
f
int
0
0
1
1
0
0
1
1
= f
and reverse, the best regarding duty cycle is from
XTAL
1
/
n
f
1
, the duty cycle must be ensured by the incoming clock signal on
XTAL
/
n
f
XTAL
to
40
1
to
/
2
f
1
int
/
2
f
and reverse, only the bit AC2 must be changed (AC1
int
DESCRIPTION
and reverse, a delay can occur between the
AC0
0
1
0
1
0
1
0
1
1
/
n
f
XTAL
f
1
1
1
1
1
1
1
or
XTAL
/
/
/
/
/
/
/
2
4
8
2
2
2
2
f
f
f
f
f
f
f
1
XTAL
XTAL
XTAL
int
int
int
int
/
2
f
1
int
/
8
Product specification
f
to stopped clock
XTAL
CLOCK
TDA8029
to
1
/
2
f
int
and