74AUP1G386 NXP Semiconductors, 74AUP1G386 Datasheet

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74AUP1G386

Manufacturer Part Number
74AUP1G386
Description
Low-power 3-input EXCLUSIVE-OR gate
Manufacturer
NXP Semiconductors
Datasheet
1. General description
2. Features
The 74AUP1G386 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial power-down applications using I
The I
the device when it is powered down.
The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.
CC
74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
Rev. 02 — 10 January 2008
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
range from 0.8 V to 3.6 V.
OFF
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114E Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101-C exceeds 1000 V
circuitry provides partial Power-down mode operation
circuitry disables the output, preventing the damaging backflow current through
CC
range from 0.8 V to 3.6 V.
CC
= 0.9 A (maximum)
CC
www.DataSheet4U.com
Product data sheet
OFF
.

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74AUP1G386 Summary of contents

Page 1

... Low-power 3-input EXCLUSIVE-OR gate Rev. 02 — 10 January 2008 1. General description The 74AUP1G386 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V ...

Page 2

... Type number Package Temperature range Name 74AUP1G386GW +125 C 74AUP1G386GM +125 C 74AUP1G386GF +125 C 4. Marking Table 2. Marking Type number 74AUP1G386GW 74AUP1G386GM 74AUP1G386GF 5. Functional diagram mnb143 Fig 1. Logic symbol Fig 3. Logic diagram 74AUP1G386_2 Product data sheet ...

Page 3

... Y 001aad939 Transparent top view Fig 5. Pin configuration SOT886 (XSON6 Rev. 02 — 10 January 2008 74AUP1G386 74AUP1G386 GND 001aad938 Transparent top view Fig 6. Pin configuration SOT891 (XSON6) Output ...

Page 4

... Active mode and Power-down mode +125 C amb derates linearly with 4.0 mW/K. tot derates linearly with 2.4 mW/K. tot Conditions Active mode Power-down mode 0 3 Rev. 02 — 10 January 2008 74AUP1G386 www.DataSheet4U.com Min Max Unit 0.5 +4 [1] 0.5 +4 [1] 0.5 +4.6 ...

Page 5

... GND GND Rev. 02 — 10 January 2008 74AUP1G386 www.DataSheet4U.com Low-power 3-input EXCLUSIVE-OR gate Min Typ Max ...

Page 6

... 3 0 GND Rev. 02 — 10 January 2008 74AUP1G386 www.DataSheet4U.com Low-power 3-input EXCLUSIVE-OR gate Min Typ Max 0.7 ...

Page 7

... 3 0 GND Rev. 02 — 10 January 2008 74AUP1G386 www.DataSheet4U.com Low-power 3-input EXCLUSIVE-OR gate Min Typ Max 0.7 ...

Page 8

... Figure 1.3 V 3 1.6 V 2 1.95 V 2 2.7 V 2 3.6 V 2.0 [2] Figure 1.3 V 4 1.6 V 3 1.95 V 3 2.7 V 2 3.6 V 2.7 Rev. 02 — 10 January 2008 74AUP1G386 www.DataSheet4U.com Low-power 3-input EXCLUSIVE-OR gate +125 C [1] Typ Max Min Max (85 C) (125 C) 23 6.5 14.2 2.4 14.6 4.4 8.1 2.1 8.8 3.5 6.1 1.6 7 ...

Page 9

... input GND t PHL output phase PLH output Table 9. Rev. 02 — 10 January 2008 74AUP1G386 www.DataSheet4U.com Low-power 3-input EXCLUSIVE-OR gate +125 C [1] Typ Max Min Max (85 C) (125 ...

Page 10

... DUT for measuring propagation delays, setup and hold times and pulse width R L Rev. 02 — 10 January 2008 74AUP1G386 www.DataSheet4U.com Low-power 3-input EXCLUSIVE-OR gate 3 EXT 001aac521 of the pulse generator ...

Page 11

... scale 2.2 1.35 2.2 0.45 1.3 0.65 1.8 1.15 2.0 0.15 REFERENCES JEDEC JEITA SC-88 Rev. 02 — 10 January 2008 74AUP1G386 www.DataSheet4U.com Low-power 3-input EXCLUSIVE-OR gate detail 0.25 0.2 0.2 0.1 0.15 EUROPEAN ISSUE DATE PROJECTION © NXP B.V. 2008. All rights reserved. SOT363 ...

Page 12

... scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA MO-252 Rev. 02 — 10 January 2008 74AUP1G386 www.DataSheet4U.com Low-power 3-input EXCLUSIVE-OR gate 4 ( EUROPEAN PROJECTION © NXP B.V. 2008. All rights reserved. SOT886 ISSUE DATE 04-07-15 04-07- ...

Page 13

... Product data sheet scale 1.05 0.35 0.40 0.55 0.35 0.95 0.27 0.32 REFERENCES JEDEC JEITA Rev. 02 — 10 January 2008 74AUP1G386 www.DataSheet4U.com Low-power 3-input EXCLUSIVE-OR gate 4 ( EUROPEAN ISSUE DATE PROJECTION 05-04-06 07-05-15 © NXP B.V. 2008. All rights reserved. SOT891 ...

Page 14

... ESD HBM value modified in 74AUP1G386_1 20061129 74AUP1G386_2 Product data sheet Low-power 3-input EXCLUSIVE-OR gate Data sheet status Change notice Product data sheet - Section 2 Product data sheet - Rev. 02 — 10 January 2008 74AUP1G386 www.DataSheet4U.com Supersedes 74AUP1G386_1 - © NXP B.V. 2008. All rights reserved ...

Page 15

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 10 January 2008 74AUP1G386 www.DataSheet4U.com Low-power 3-input EXCLUSIVE-OR gate © NXP B.V. 2008. All rights reserved ...

Page 16

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: 74AUP1G386_2 All rights reserved. Date of release: 10 January 2008 ...

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