IDT72255LA10PF IDT, Integrated Device Technology Inc, IDT72255LA10PF Datasheet - Page 2

• Manufacturer Part Number: IDT72255LA10PF
• Description: IC FIFO SUPERSYNC 8KX18 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72255LA10PF

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Access Time: 10ns
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 8ns
• Word Size: 18b
• Organization: 8Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 80mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72255LA10PF; 800-1499

DESCRIPTION (CONTINUED)
PIN CONFIGURATIONS
telecommunications, data communications and other applications that need to
buffer large amounts of data.
(WEN) input. Data is written into the FIFO on every rising edge of WCLK when
WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
and Read Enable (REN) input. Data is read from the FIFO on every rising edge
of RCLK when REN is asserted. An Output Enable (OE) input is provided for
three-state control of the outputs.
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
NOTE:
1. DC = Don’t Care. Must be tied to GND or V
SuperSync FIFOs are particularly appropriate for networking, video,
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
PIN 1
WEN
GND
SEN
D17
D16
D15
D14
D13
D12
D11
D10
V
DC
D9
D8
D7
CC
CC
, cannot be left open.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
STQFP (PP64-1, ORDER CODE: TF)
TQFP (PN64-1, ORDER CODE: PF)
TOP VIEW
2
to f
of one clock input with respect to the other.
Standard mode and First Word Fall Through (FWFT) mode.
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
The frequencies of both the RCLK and the WCLK signals may vary from 0
In IDT Standard mode, the first word written to an empty FIFO will not appear
MAX
There are two possible timing modes of operation with these devices: IDT
with complete independence. There are no restrictions on the frequency
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMMERCIAL AND INDUSTRIAL
4670 drw02
TEMPERATURE RANGES
Q17
Q16
GND
Q15
Q14
V
Q13
Q12
Q11
GND
Q10
Q9
Q8
Q7
Q6
GND
CC
JANUARY 13, 2009