74HCT40105DB,118 NXP Semiconductors, 74HCT40105DB,118 Datasheet - Page 12
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74HCT40105DB,118
Manufacturer Part Number
74HCT40105DB,118
Description
IC FIFO REGISTER 4X16 16SSOP
Manufacturer
NXP Semiconductors
Series
74HCTr
Datasheet
1.74HC40105DB118.pdf
(25 pages)
Specifications of 74HCT40105DB,118
Function
Asynchronous
Memory Size
64 (4 x 16)
Data Rate
25MHz
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
16-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Access Time
-
Other names
74HCT40105DB-T
74HCT40105DB-T
935189960118
74HCT40105DB-T
935189960118
Philips Semiconductors
Master reset applied with FIFO full
Shifting out sequence; FIFO full to FIFO empty
1998 Jan 23
4-bit x 16-word FIFO register
(1) HC : V
Fig.8
(1) HC : V
Fig.9
HCT : V
HCT : V
Waveforms showing the MR input to DIR, DOR output
propagation delays and the MR pulse width.
Waveforms showing the SO input to DIR output propagation
delay. The SO pulse width and SO maximum pulse frequency.
M
M
M
M
= 50%; V
= 50%; V
= 1.3 V; V
= 1.3 V; V
I
I
I
I
= GND to V
= GND to V
= GND to 3 V.
= GND to 3 V.
CC
CC
.
.
12
Notes to Fig.8
1. DIR LOW, output ready HIGH;
2. MR pulse HIGH; clears FIFO.
3. DIR goes HIGH; flag indicates
4. DOR drops LOW; flag indicates
Notes to Fig.9
1. DOR HIGH; no data transfer in
2. SO set HIGH.
3. SO is set LOW; data in the input
4. DOR drops LOW; output stage
5. DOR goes HIGH; transfer
6. Repeat process to unloaded the
7. DOR remains LOW; FIFO is
assume FIFO is full.
input prepared for valid data.
FIFO empty.
progress, valid data is present at
output stage.
stage is unloaded, and new data
replaces it as empty location
“bubbles-up” to input stage.
“busy”.
process completed, valid data
present at output after the
specified propagation delay.
3rd through to the 16th word from
FIFO.
empty.
74HC/HCT40105
Product specification